[Qemu-devel] [PATCH v3 0/8] target-sh4: optimizations and cleanups

[Aurelien Jarno <aurelien@aurel32.net>]

This patchset improves the SH4 emulation by using the recently added
TCG instructions, namely add2, sub2 and movcond. For that the T, Q and
M bits are split out from the SR register. This allow the optimizer and
the liveness analysis to do some more optimisations.

The last two patches are doing cleanup in the code.

Changes v2 -> v3:
- rebased
- patch 2: don't mask out T bit from env->sr when reading
- patch 6: don't mask out Q and M bits from env->sr when reading
           correctly compute M bit in div0s
           add some comments to explain the tricks used in div1

Changes v1 -> v2:
- rebased
- added last patch

Aurelien Jarno (8):
  target-sh4: use bit number for SR constants
  target-sh4: Split out T from SR
  target-sh4: optimize addc using add2
  target-sh4: optimize subc using sub2
  target-sh4: optimize negc using add2 and sub2
  target-sh4: split out Q and M from of SR and optimize div1
  target-sh4: factorize fmov implementation
  target-sh4: remove dead code

 target-sh4/cpu.c       |   3 +-
 target-sh4/cpu.h       |  50 +++++---
 target-sh4/gdbstub.c   |   8 +-
 target-sh4/helper.c    |  29 ++---
 target-sh4/helper.h    |   1 -
 target-sh4/op_helper.c | 148 +-----------------------
 target-sh4/translate.c | 307 +++++++++++++++++++++++++------------------------
 7 files changed, 217 insertions(+), 329 deletions(-)

-- 
2.1.4