[Qemu-devel] [PATCH v2 00/14] arm: Steps towards EL2 support round 3

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Hi,

This is round 3 of our series towards support for EL2 for AArch64.
This series depends on Gregs and Peters exception target el infrastructure
patch series that is not yet upstream.

While adding the AArch32 versions of some of these regs I ran into
issues with the overly broad definition of TLB_LOCKDOWN. I broke it
down somewhat to v7 level.

Comments welcome!

Best regards,
Edgar

v1 -> v2:
* Drop PAR_EL1
* Add AArch32 mappings of MAIR_EL2
* Add AArch32 mappings of TCR_EL2
* Add AArch32 mappings of SCTLR_EL2
* Add AArch32 mappings of TTBR0_EL2
* Add AArch32 mappings of TPIDR_EL2
* Add AArch32 mappings of CNTHCTL_EL2
* Add AArch32 mappings of CNTVOFF_EL2
* Tag CNTVOFF_EL2 and CNTVOFF as ARM_CP_IO
* Rename TLIBALLE2 -> TLBI_ALLE2
* Break down TLB_LOCKDOWN to v7 level

Edgar E. Iglesias (14):
  target-arm: Break down TLB_LOCKDOWN
  target-arm: Add MAIR_EL2
  target-arm: Add TCR_EL2
  target-arm: Add SCTLR_EL2
  target-arm: Add TPIDR_EL2
  target-arm: Add TTBR0_EL2
  target-arm: Add TLBI_ALLE1{IS}
  target-arm: Add TLBI_ALLE2
  target-arm: Add TLBI_VAE2{IS}
  target-arm: Add CNTVOFF_EL2
  target-arm: Add CNTHCTL_EL2
  target-arm: Pass timeridx as argument to various timer functions
  target-arm: Add HYP timer
  hw/arm/virt: Connect the Hypervisor timer

 hw/arm/virt.c        |   3 +
 target-arm/cpu-qom.h |   1 +
 target-arm/cpu.c     |   2 +
 target-arm/cpu.h     |   5 +-
 target-arm/helper.c  | 340 ++++++++++++++++++++++++++++++++++++++++++++-------
 5 files changed, 309 insertions(+), 42 deletions(-)

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1.9.1