From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVru-0003pw-58 for qemu-devel@nongnu.org; Wed, 27 May 2015 03:35:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxVrl-0006QF-Sx for qemu-devel@nongnu.org; Wed, 27 May 2015 03:35:14 -0400 Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]:36121) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVrl-0006MH-J7 for qemu-devel@nongnu.org; Wed, 27 May 2015 03:35:05 -0400 Received: by pdfh10 with SMTP id h10so2898699pdf.3 for ; Wed, 27 May 2015 00:35:04 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 27 May 2015 17:27:30 +1000 Message-Id: <1432711659-24591-6-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> References: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 05/14] target-arm: Add TPIDR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 334e008..df07a6a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2530,6 +2530,9 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -2618,6 +2621,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, + { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0, + .access = PL2_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, REGINFO_SENTINEL }; -- 1.9.1