From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVsz-0005EF-Tf for qemu-devel@nongnu.org; Wed, 27 May 2015 03:36:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxVsu-0006wH-Hs for qemu-devel@nongnu.org; Wed, 27 May 2015 03:36:21 -0400 Received: from mail-pd0-x230.google.com ([2607:f8b0:400e:c02::230]:34681) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxVsu-0006vj-9R for qemu-devel@nongnu.org; Wed, 27 May 2015 03:36:16 -0400 Received: by pdbki1 with SMTP id ki1so3127525pdb.1 for ; Wed, 27 May 2015 00:36:15 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 27 May 2015 17:27:32 +1000 Message-Id: <1432711659-24591-8-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> References: <1432711659-24591-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 07/14] target-arm: Add TLBI_ALLE1{IS} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 193750b..826df50 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2368,6 +2368,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, .access = PL1_W, .type = ARM_CP_NOP }, /* TLBI operations */ + { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbiall_write }, + { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbiall_write }, { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW, -- 1.9.1