From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxaN5-0005xa-K2 for qemu-devel@nongnu.org; Wed, 27 May 2015 08:23:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxaN0-0002rU-Uc for qemu-devel@nongnu.org; Wed, 27 May 2015 08:23:43 -0400 Received: from smtp2-g21.free.fr ([2a01:e0c:1:1599::11]:33143) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxaN0-0002qX-LN for qemu-devel@nongnu.org; Wed, 27 May 2015 08:23:38 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Wed, 27 May 2015 14:19:53 +0200 Message-Id: <1432729200-5322-11-git-send-email-hpoussin@reactos.org> In-Reply-To: <1432729200-5322-1-git-send-email-hpoussin@reactos.org> References: <1432729200-5322-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 10/17] net/dp8393x: use dp8393x_ prefix for all functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Leon Alrae , Aurelien Jarno Signed-off-by: Herv=C3=A9 Poussineau --- hw/net/dp8393x.c | 80 +++++++++++++++++++++++++++++---------------------= ------ 1 file changed, 41 insertions(+), 39 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 5cc1e6b..0aff04f 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -183,7 +183,7 @@ static void dp8393x_update_irq(dp8393xState *s) qemu_set_irq(s->irq, level); } =20 -static void do_load_cam(dp8393xState *s) +static void dp8393x_do_load_cam(dp8393xState *s) { uint16_t data[8]; int width, size; @@ -225,7 +225,7 @@ static void do_load_cam(dp8393xState *s) dp8393x_update_irq(s); } =20 -static void do_read_rra(dp8393xState *s) +static void dp8393x_do_read_rra(dp8393xState *s) { uint16_t data[8]; int width, size; @@ -265,7 +265,7 @@ static void do_read_rra(dp8393xState *s) s->regs[SONIC_CR] &=3D ~SONIC_CR_RRRA; } =20 -static void do_software_reset(dp8393xState *s) +static void dp8393x_do_software_reset(dp8393xState *s) { timer_del(s->watchdog); =20 @@ -273,7 +273,7 @@ static void do_software_reset(dp8393xState *s) s->regs[SONIC_CR] |=3D SONIC_CR_RST | SONIC_CR_RXDIS; } =20 -static void set_next_tick(dp8393xState *s) +static void dp8393x_set_next_tick(dp8393xState *s) { uint32_t ticks; int64_t delay; @@ -289,7 +289,7 @@ static void set_next_tick(dp8393xState *s) timer_mod(s->watchdog, s->wt_last_update + delay); } =20 -static void update_wt_regs(dp8393xState *s) +static void dp8393x_update_wt_regs(dp8393xState *s) { int64_t elapsed; uint32_t val; @@ -304,33 +304,33 @@ static void update_wt_regs(dp8393xState *s) val -=3D elapsed / 5000000; s->regs[SONIC_WT1] =3D (val >> 16) & 0xffff; s->regs[SONIC_WT0] =3D (val >> 0) & 0xffff; - set_next_tick(s); + dp8393x_set_next_tick(s); =20 } =20 -static void do_start_timer(dp8393xState *s) +static void dp8393x_do_start_timer(dp8393xState *s) { s->regs[SONIC_CR] &=3D ~SONIC_CR_STP; - set_next_tick(s); + dp8393x_set_next_tick(s); } =20 -static void do_stop_timer(dp8393xState *s) +static void dp8393x_do_stop_timer(dp8393xState *s) { s->regs[SONIC_CR] &=3D ~SONIC_CR_ST; - update_wt_regs(s); + dp8393x_update_wt_regs(s); } =20 -static void do_receiver_enable(dp8393xState *s) +static void dp8393x_do_receiver_enable(dp8393xState *s) { s->regs[SONIC_CR] &=3D ~SONIC_CR_RXDIS; } =20 -static void do_receiver_disable(dp8393xState *s) +static void dp8393x_do_receiver_disable(dp8393xState *s) { s->regs[SONIC_CR] &=3D ~SONIC_CR_RXEN; } =20 -static void do_transmit_packets(dp8393xState *s) +static void dp8393x_do_transmit_packets(dp8393xState *s) { NetClientState *nc =3D qemu_get_queue(s->nic); uint16_t data[12]; @@ -439,12 +439,12 @@ static void do_transmit_packets(dp8393xState *s) dp8393x_update_irq(s); } =20 -static void do_halt_transmission(dp8393xState *s) +static void dp8393x_do_halt_transmission(dp8393xState *s) { /* Nothing to do */ } =20 -static void do_command(dp8393xState *s, uint16_t command) +static void dp8393x_do_command(dp8393xState *s, uint16_t command) { if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST))= { s->regs[SONIC_CR] &=3D ~SONIC_CR_RST; @@ -454,23 +454,23 @@ static void do_command(dp8393xState *s, uint16_t co= mmand) s->regs[SONIC_CR] |=3D (command & SONIC_CR_MASK); =20 if (command & SONIC_CR_HTX) - do_halt_transmission(s); + dp8393x_do_halt_transmission(s); if (command & SONIC_CR_TXP) - do_transmit_packets(s); + dp8393x_do_transmit_packets(s); if (command & SONIC_CR_RXDIS) - do_receiver_disable(s); + dp8393x_do_receiver_disable(s); if (command & SONIC_CR_RXEN) - do_receiver_enable(s); + dp8393x_do_receiver_enable(s); if (command & SONIC_CR_STP) - do_stop_timer(s); + dp8393x_do_stop_timer(s); if (command & SONIC_CR_ST) - do_start_timer(s); + dp8393x_do_start_timer(s); if (command & SONIC_CR_RST) - do_software_reset(s); + dp8393x_do_software_reset(s); if (command & SONIC_CR_RRRA) - do_read_rra(s); + dp8393x_do_read_rra(s); if (command & SONIC_CR_LCAM) - do_load_cam(s); + dp8393x_do_load_cam(s); } =20 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int siz= e) @@ -483,7 +483,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr add= r, unsigned int size) /* Update data before reading it */ case SONIC_WT0: case SONIC_WT1: - update_wt_regs(s); + dp8393x_update_wt_regs(s); val =3D s->regs[reg]; break; /* Accept read to some registers only when in reset mode */ @@ -516,7 +516,7 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, switch (reg) { /* Command register */ case SONIC_CR: - do_command(s, data); + dp8393x_do_command(s, data); break; /* Prevent write to read-only registers */ case SONIC_CAP2: @@ -559,7 +559,7 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, data &=3D s->regs[reg]; s->regs[reg] &=3D ~data; if (data & SONIC_ISR_RBE) { - do_read_rra(s); + dp8393x_do_read_rra(s); } dp8393x_update_irq(s); break; @@ -582,7 +582,7 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, } =20 if (reg =3D=3D SONIC_WT0 || reg =3D=3D SONIC_WT1) { - set_next_tick(s); + dp8393x_set_next_tick(s); } } =20 @@ -604,14 +604,14 @@ static void dp8393x_watchdog(void *opaque) =20 s->regs[SONIC_WT1] =3D 0xffff; s->regs[SONIC_WT0] =3D 0xffff; - set_next_tick(s); + dp8393x_set_next_tick(s); =20 /* Signal underflow */ s->regs[SONIC_ISR] |=3D SONIC_ISR_TC; dp8393x_update_irq(s); } =20 -static int nic_can_receive(NetClientState *nc) +static int dp8393x_can_receive(NetClientState *nc) { dp8393xState *s =3D qemu_get_nic_opaque(nc); =20 @@ -622,7 +622,8 @@ static int nic_can_receive(NetClientState *nc) return 1; } =20 -static int receive_filter(dp8393xState *s, const uint8_t * buf, int size= ) +static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, + int size) { static const uint8_t bcast[] =3D {0xff, 0xff, 0xff, 0xff, 0xff, 0xff= }; int i; @@ -660,7 +661,8 @@ static int receive_filter(dp8393xState *s, const uint= 8_t * buf, int size) return -1; } =20 -static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size= _t size) +static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, + size_t size) { dp8393xState *s =3D qemu_get_nic_opaque(nc); uint16_t data[10]; @@ -674,7 +676,7 @@ static ssize_t nic_receive(NetClientState *nc, const = uint8_t * buf, size_t size) s->regs[SONIC_RCR] &=3D ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_= FAER | SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); =20 - packet_type =3D receive_filter(s, buf, size); + packet_type =3D dp8393x_receive_filter(s, buf, size); if (packet_type < 0) { DPRINTF("packet not for netcard\n"); return -1; @@ -762,7 +764,7 @@ static ssize_t nic_receive(NetClientState *nc, const = uint8_t * buf, size_t size) =20 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { /* Read next RRA */ - do_read_rra(s); + dp8393x_do_read_rra(s); } } =20 @@ -772,7 +774,7 @@ static ssize_t nic_receive(NetClientState *nc, const = uint8_t * buf, size_t size) return size; } =20 -static void nic_reset(void *opaque) +static void dp8393x_reset(void *opaque) { dp8393xState *s =3D opaque; timer_del(s->watchdog); @@ -799,8 +801,8 @@ static void nic_reset(void *opaque) static NetClientInfo net_dp83932_info =3D { .type =3D NET_CLIENT_OPTIONS_KIND_NIC, .size =3D sizeof(NICState), - .can_receive =3D nic_can_receive, - .receive =3D nic_receive, + .can_receive =3D dp8393x_can_receive, + .receive =3D dp8393x_receive, }; =20 void dp83932_init(NICInfo *nd, hwaddr base, int it_shift, @@ -826,8 +828,8 @@ void dp83932_init(NICInfo *nd, hwaddr base, int it_sh= ift, s->nic =3D qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->= name, s); =20 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); - qemu_register_reset(nic_reset, s); - nic_reset(s); + qemu_register_reset(dp8393x_reset, s); + dp8393x_reset(s); =20 memory_region_init_io(&s->mmio, NULL, &dp8393x_ops, s, "dp8393x", 0x40 << it_shift); --=20 2.1.4