From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: qemu-devel@nongnu.org
Cc: Sai Pavan Boddu <saipava@xilinx.com>,
edgari@xilinx.com, alistai@xilinx.com, pcrost@xilinx.com
Subject: [Qemu-devel] [PATCH V1] cadence_gem: Fix Rx buffer size field mask
Date: Fri, 29 May 2015 11:52:35 +0530 [thread overview]
Message-ID: <1432880555-21080-1-git-send-email-saipava@xilinx.com> (raw)
This patch corrects the Rx buffer size field mask to mask bits 23 to 16
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/net/cadence_gem.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index dafe914..494a346 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -155,7 +155,7 @@
#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
-#define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */
+#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
--
1.7.4
next reply other threads:[~2015-05-29 7:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-29 6:22 Sai Pavan Boddu [this message]
2015-06-01 2:51 ` [Qemu-devel] [PATCH V1] cadence_gem: Fix Rx buffer size field mask Peter Crosthwaite
2015-06-02 8:32 ` Michael Tokarev
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