From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyE7b-0001lx-3g for qemu-devel@nongnu.org; Fri, 29 May 2015 02:50:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyE7X-0001dZ-Qt for qemu-devel@nongnu.org; Fri, 29 May 2015 02:50:23 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:33445) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyE7X-0001dK-Kq for qemu-devel@nongnu.org; Fri, 29 May 2015 02:50:19 -0400 Received: by padbw4 with SMTP id bw4so45911136pad.0 for ; Thu, 28 May 2015 23:50:18 -0700 (PDT) From: "Edgar E. Iglesias" Date: Fri, 29 May 2015 16:43:16 +1000 Message-Id: <1432881807-18164-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1432881807-18164-1-git-send-email-edgar.iglesias@gmail.com> References: <1432881807-18164-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v3 04/15] target-arm: Add TCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 427cfab..7dadc8a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2524,6 +2524,9 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -2603,6 +2606,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, + { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, + .access = PL2_RW, .writefn = vmsa_tcr_el1_write, + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, REGINFO_SENTINEL }; -- 1.9.1