From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyiFC-0000vn-Mz for qemu-devel@nongnu.org; Sat, 30 May 2015 11:00:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyiF6-0006eL-VG for qemu-devel@nongnu.org; Sat, 30 May 2015 11:00:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:51243) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyiF6-0006WV-P8 for qemu-devel@nongnu.org; Sat, 30 May 2015 11:00:08 -0400 From: Bastian Koppelmann Date: Sat, 30 May 2015 16:59:51 +0200 Message-Id: <1432997993-25533-2-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1432997993-25533-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1432997993-25533-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org If the argument r1 was the same as the extended result register r3+1, we would overwrite r1 and then use it. Signed-off-by: Bastian Koppelmann Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de> --- target-tricore/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 5f8eff0..6c14843 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6451,8 +6451,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) /* sv */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); /* write result */ - tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); + tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_temp_free(temp); tcg_temp_free(temp2); tcg_temp_free(temp3); -- 2.4.2