[Qemu-devel] [PULL 0/3] tricore-patches

[Qemu-devel] [PULL 0/3] tricore-patches

[Bastian Koppelmann]

The following changes since commit 97af820f539efe80b87615a04f9de11ea585f725:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150529' into staging (2015-05-29 17:10:57 +0100)

are available in the git repository at:

  https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150530

for you to fetch changes up to 07e15486faf353260431f10e85185372c5036baa:

  target-tricore: fix BOL_ST_H_LONGOFF using ld (2015-05-30 16:49:19 +0200)

----------------------------------------------------------------
TriCore bugfixes

----------------------------------------------------------------
Bastian Koppelmann (3):
      target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
      target-tricore: fix msub32_q producing the wrong overflow bit
      target-tricore: fix BOL_ST_H_LONGOFF using ld

 target-tricore/translate.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)
-- 
2.4.2

[Qemu-devel] [PULL 1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result

[Bastian Koppelmann]

If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5f8eff0..6c14843 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6451,8 +6451,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
         /* sv */
         tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
         /* write result */
-        tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
         tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
+        tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
         tcg_temp_free(temp);
         tcg_temp_free(temp2);
         tcg_temp_free(temp3);
-- 
2.4.2

[Qemu-devel] [PULL 2/3] target-tricore: fix msub32_q producing the wrong overflow bit

[Bastian Koppelmann]

The inversion of the overflow bit as a special case, which was needed for the
madd32_q instructions, does not apply for msub32_q instructions. So remove it.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1432289758-6250-3-git-send-email-kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 6c14843..8560d00 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -1980,17 +1980,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
     tcg_gen_or_i64(t1, t1, t2);
     tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
     tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
-    /* We produce an overflow on the host if the mul before was
-       (0x80000000 * 0x80000000) << 1). If this is the
-       case, we negate the ovf. */
-    if (n == 1) {
-        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
-        tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
-        tcg_gen_and_tl(temp, temp, temp2);
-        tcg_gen_shli_tl(temp, temp, 31);
-        /* negate v bit, if special condition */
-        tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
-    }
     /* Calc SV bit */
     tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
     /* Calc AV/SAV bits */
-- 
2.4.2

[Qemu-devel] [PULL 3/3] target-tricore: fix BOL_ST_H_LONGOFF using ld

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1432289758-6250-4-git-send-email-kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 8560d00..8d41239 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -5276,7 +5276,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
         break;
     case OPC1_32_BOL_ST_H_LONGOFF:
         if (tricore_feature(env, TRICORE_FEATURE_16)) {
-            gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
+            gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
         } else {
             /* raise illegal opcode trap */
         }
-- 
2.4.2

Re: [Qemu-devel] [PULL 0/3] tricore-patches

[Peter Maydell]

On 30 May 2015 at 15:59, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
> The following changes since commit 97af820f539efe80b87615a04f9de11ea585f725:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150529' into staging (2015-05-29 17:10:57 +0100)
>
> are available in the git repository at:
>
>   https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150530
>
> for you to fetch changes up to 07e15486faf353260431f10e85185372c5036baa:
>
>   target-tricore: fix BOL_ST_H_LONGOFF using ld (2015-05-30 16:49:19 +0200)
>
> ----------------------------------------------------------------
> TriCore bugfixes

Applied, thanks.

-- PMM