From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55530) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyiFB-0000vZ-MG for qemu-devel@nongnu.org; Sat, 30 May 2015 11:00:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyiF7-0006f5-8x for qemu-devel@nongnu.org; Sat, 30 May 2015 11:00:13 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:51259) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyiF7-0006Xf-2m for qemu-devel@nongnu.org; Sat, 30 May 2015 11:00:09 -0400 From: Bastian Koppelmann Date: Sat, 30 May 2015 16:59:52 +0200 Message-Id: <1432997993-25533-3-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1432997993-25533-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1432997993-25533-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 2/3] target-tricore: fix msub32_q producing the wrong overflow bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The inversion of the overflow bit as a special case, which was needed for the madd32_q instructions, does not apply for msub32_q instructions. So remove it. Signed-off-by: Bastian Koppelmann Message-Id: <1432289758-6250-3-git-send-email-kbastian@mail.uni-paderborn.de> --- target-tricore/translate.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 6c14843..8560d00 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -1980,17 +1980,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, tcg_gen_or_i64(t1, t1, t2); tcg_gen_trunc_i64_i32(cpu_PSW_V, t1); tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); - /* We produce an overflow on the host if the mul before was - (0x80000000 * 0x80000000) << 1). If this is the - case, we negate the ovf. */ - if (n == 1) { - tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); - tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); - tcg_gen_and_tl(temp, temp, temp2); - tcg_gen_shli_tl(temp, temp, 31); - /* negate v bit, if special condition */ - tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); - } /* Calc SV bit */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); /* Calc AV/SAV bits */ -- 2.4.2