From: Victor CLEMENT <victor.clement@openwide.fr>
To: qemu-devel@nongnu.org
Cc: Victor CLEMENT <victor.clement@openwide.fr>,
julien.viarddegalbert@openwide.fr
Subject: [Qemu-devel] [PATCH 1/1] pl061: fix wrong calculation of GPIOMIS register
Date: Mon, 1 Jun 2015 12:33:44 +0200 [thread overview]
Message-ID: <1433154824-6927-1-git-send-email-victor.clement@openwide.fr> (raw)
The masked interrupt status register should be the state of the interrupt
after masking.
There should be a logical AND instead of a logical OR between the
interrupt status and the interrupt mask.
Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr>
---
See ARM PrimeCell GPIO manual below
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0190b/I36092.html
---
hw/gpio/pl061.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index bd03e99..4ba730b 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -173,7 +173,7 @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
case 0x414: /* Raw interrupt status */
return s->istate;
case 0x418: /* Masked interrupt status */
- return s->istate | s->im;
+ return s->istate & s->im;
case 0x420: /* Alternate function select */
return s->afsel;
case 0x500: /* 2mA drive */
--
2.3.7
next reply other threads:[~2015-06-01 10:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-01 10:33 Victor CLEMENT [this message]
2015-06-01 10:47 ` [Qemu-devel] [PATCH 1/1] pl061: fix wrong calculation of GPIOMIS register Peter Crosthwaite
2015-06-01 17:22 ` Peter Maydell
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