From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzN2Z-00022M-CG for qemu-devel@nongnu.org; Mon, 01 Jun 2015 06:33:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzN2V-0007vX-CQ for qemu-devel@nongnu.org; Mon, 01 Jun 2015 06:33:55 -0400 Received: from zimbra3.corp.accelance.fr ([2001:4080:204::2:8]:40283) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzN2V-0007uW-73 for qemu-devel@nongnu.org; Mon, 01 Jun 2015 06:33:51 -0400 Received: from localhost (localhost [127.0.0.1]) by zimbra3.corp.accelance.fr (Postfix) with ESMTP id 2DFBF7DE30 for ; Mon, 1 Jun 2015 12:33:49 +0200 (CEST) From: Victor CLEMENT Date: Mon, 1 Jun 2015 12:33:44 +0200 Message-Id: <1433154824-6927-1-git-send-email-victor.clement@openwide.fr> Subject: [Qemu-devel] [PATCH 1/1] pl061: fix wrong calculation of GPIOMIS register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Victor CLEMENT , julien.viarddegalbert@openwide.fr The masked interrupt status register should be the state of the interrupt after masking. There should be a logical AND instead of a logical OR between the interrupt status and the interrupt mask. Signed-off-by: Victor CLEMENT --- See ARM PrimeCell GPIO manual below http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0190b/I36092.html --- hw/gpio/pl061.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index bd03e99..4ba730b 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -173,7 +173,7 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, case 0x414: /* Raw interrupt status */ return s->istate; case 0x418: /* Masked interrupt status */ - return s->istate | s->im; + return s->istate & s->im; case 0x420: /* Alternate function select */ return s->afsel; case 0x500: /* 2mA drive */ -- 2.3.7