From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzN3F-0002ps-G5 for qemu-devel@nongnu.org; Mon, 01 Jun 2015 06:34:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzN3B-00087R-Ec for qemu-devel@nongnu.org; Mon, 01 Jun 2015 06:34:37 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:33178) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzN3B-00087N-AF for qemu-devel@nongnu.org; Mon, 01 Jun 2015 06:34:33 -0400 Received: by padj3 with SMTP id j3so40661918pad.0 for ; Mon, 01 Jun 2015 03:34:32 -0700 (PDT) From: shannon.zhao@linaro.org Date: Mon, 1 Jun 2015 18:34:20 +0800 Message-Id: <1433154861-4116-2-git-send-email-shannon.zhao@linaro.org> In-Reply-To: <1433154861-4116-1-git-send-email-shannon.zhao@linaro.org> References: <1433154861-4116-1-git-send-email-shannon.zhao@linaro.org> Subject: [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: shannon.zhao@linaro.org, zhaoshenglong@huawei.com From: Shannon Zhao Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- target-arm/cpu64.c | 1 + target-arm/kvm-consts.h | 2 ++ target-arm/kvm64.c | 1 + 3 files changed, 4 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bf7dd68..dd6f9d8 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -159,6 +159,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->midr = 0x410fd034; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h index aea12f1..4c10476 100644 --- a/target-arm/kvm-consts.h +++ b/target-arm/kvm-consts.h @@ -127,6 +127,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) #define QEMU_KVM_ARM_TARGET_AEM_V8 0 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 +#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 /* There's no kernel define for this: sentinel value which * matches no KVM target value for either 64 or 32 bit @@ -137,6 +138,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53) #else MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 93c1ca8..0f1cd29 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -50,6 +50,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_CORTEX_A57, + KVM_ARM_TARGET_CORTEX_A53 = 4, QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; -- 2.1.0