[Qemu-devel] [PATCH V2] Target-arm: Add the Cortex-M4 CPU

[Qemu-devel] [PATCH V2] Target-arm: Add the Cortex-M4 CPU

[Aurelio C. Remonda]

* Changes in V2: Add the ARM_FEATURE_THUMB_DSP in a separate patch.
This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3,
the main differences being the DSP instructions and an optional FPU.
I created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible
CPU that uses DSP instructions, and I manually added it to the M4 in its initfn.

Signed-off-by: Aurelio C. Remonda <aurelioremonda@gmail.com>
---
 target-arm/cpu.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4a888ab..537e6ee 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -533,6 +533,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
         set_feature(env, ARM_FEATURE_CBAR);
     }
+    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
+        !arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_THUMB_DSP);
+    }
 
     if (cpu->reset_hivecs) {
             cpu->reset_sctlr |= (1 << 13);
@@ -782,6 +786,22 @@ static void cortex_m3_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_M);
     cpu->midr = 0x410fc231;
 }
+static void cortex_m4_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    set_feature(&cpu->env, ARM_FEATURE_V7);
+    set_feature(&cpu->env, ARM_FEATURE_M);
+    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+    cpu->midr = 0x410fc240;
+    /* Main id register CPUID bit assignments
+     * Bits    NAME        Function
+     * [31:24] IMPLEMENTER Indicates implementor: 0x41 = ARM
+     * [23:20] VARIANT     Indicates processor revision: 0x0 = Revision 0
+     * [19:16] (Constant)  Reads as 0xF
+     * [15:4]  PARTNO      Indicates part number: 0xC24 = Cortex-M4
+     * [3:0]   REVISION    Indicates patch release: 0x0 = Patch 0.
+     */
+}
 
 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 {
@@ -1185,6 +1205,8 @@ static const ARMCPUInfo arm_cpus[] = {
     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
                              .class_init = arm_v7m_class_init },
+    { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
+                             .class_init = arm_v7m_class_init },
     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1.9.1

Re: [Qemu-devel] [PATCH V2] Target-arm: Add the Cortex-M4 CPU

[Peter Maydell]

On 1 June 2015 at 15:33, Aurelio C. Remonda <aurelioremonda@gmail.com> wrote:
> * Changes in V2: Add the ARM_FEATURE_THUMB_DSP in a separate patch.
> This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3,
> the main differences being the DSP instructions and an optional FPU.
> I created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible
> CPU that uses DSP instructions, and I manually added it to the M4 in its initfn.
>
> Signed-off-by: Aurelio C. Remonda <aurelioremonda@gmail.com>
> ---
>  target-arm/cpu.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 4a888ab..537e6ee 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -533,6 +533,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>      if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
>          set_feature(env, ARM_FEATURE_CBAR);
>      }
> +    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
> +        !arm_feature(env, ARM_FEATURE_M)) {
> +        set_feature(env, ARM_FEATURE_THUMB_DSP);
> +    }

This part needs to go in the other patch, because otherwise
it will break non-M-profile Thumb2 CPUs.

thanks
-- PMM

Re: [Qemu-devel] [PATCH V2] Target-arm: Add the Cortex-M4 CPU

[Peter Crosthwaite]

On Mon, Jun 1, 2015 at 7:33 AM, Aurelio C. Remonda
<aurelioremonda@gmail.com> wrote:
> * Changes in V2: Add the ARM_FEATURE_THUMB_DSP in a separate patch.

The inter-series changelog ...

> This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3,
> the main differences being the DSP instructions and an optional FPU.
> I created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible
> CPU that uses DSP instructions, and I manually added it to the M4 in its initfn.
>
> Signed-off-by: Aurelio C. Remonda <aurelioremonda@gmail.com>
> ---

.. goes here. below the ---. This means git will strip it off when applying.

You can put any kind of little notes or questions for the reviewer
here that shouldn't be part of the formal commit msg.

Regards,
Peter

>  target-arm/cpu.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 4a888ab..537e6ee 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -533,6 +533,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>      if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
>          set_feature(env, ARM_FEATURE_CBAR);
>      }
> +    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
> +        !arm_feature(env, ARM_FEATURE_M)) {
> +        set_feature(env, ARM_FEATURE_THUMB_DSP);
> +    }
>
>      if (cpu->reset_hivecs) {
>              cpu->reset_sctlr |= (1 << 13);
> @@ -782,6 +786,22 @@ static void cortex_m3_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_M);
>      cpu->midr = 0x410fc231;
>  }
> +static void cortex_m4_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
> +    set_feature(&cpu->env, ARM_FEATURE_V7);
> +    set_feature(&cpu->env, ARM_FEATURE_M);
> +    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
> +    cpu->midr = 0x410fc240;
> +    /* Main id register CPUID bit assignments
> +     * Bits    NAME        Function
> +     * [31:24] IMPLEMENTER Indicates implementor: 0x41 = ARM
> +     * [23:20] VARIANT     Indicates processor revision: 0x0 = Revision 0
> +     * [19:16] (Constant)  Reads as 0xF
> +     * [15:4]  PARTNO      Indicates part number: 0xC24 = Cortex-M4
> +     * [3:0]   REVISION    Indicates patch release: 0x0 = Patch 0.
> +     */
> +}
>
>  static void arm_v7m_class_init(ObjectClass *oc, void *data)
>  {
> @@ -1185,6 +1205,8 @@ static const ARMCPUInfo arm_cpus[] = {
>      { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
>      { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
>                               .class_init = arm_v7m_class_init },
> +    { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
> +                             .class_init = arm_v7m_class_init },
>      { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
>      { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
>      { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
> 1.9.1
>
>