From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzhmV-0006VM-EI for qemu-devel@nongnu.org; Tue, 02 Jun 2015 04:42:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzhmR-00073i-R1 for qemu-devel@nongnu.org; Tue, 02 Jun 2015 04:42:43 -0400 Received: from mail-lb0-x22a.google.com ([2a00:1450:4010:c04::22a]:36126) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzhmR-000736-J9 for qemu-devel@nongnu.org; Tue, 02 Jun 2015 04:42:39 -0400 Received: by lbbqq2 with SMTP id qq2so99773023lbb.3 for ; Tue, 02 Jun 2015 01:42:38 -0700 (PDT) From: Sergey Fedorov Date: Tue, 2 Jun 2015 11:42:24 +0300 Message-Id: <1433234544-26351-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH v2] target-arm: use extended address bits from supersection short descriptor List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Sergey Fedorov Since ARMv7 with LPAE support, a supersection short translation table descriptor has had extended base address fields which hold bits 39:32 of translated address. These fields are IMPDEF in ARMv6 and ARMv7 without LPAE support. Signed-off-by: Sergey Fedorov --- target-arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1cc4993..0a97312 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5323,6 +5323,8 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, if (desc & (1 << 18)) { /* Supersection. */ phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); + phys_addr |= ((uint64_t)extract32(desc, 20, 4) << 32); + phys_addr |= ((uint64_t)extract32(desc, 5, 4) << 36); *page_size = 0x1000000; } else { /* Section. */ -- 1.9.1