From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzntF-000855-Hq for qemu-devel@nongnu.org; Tue, 02 Jun 2015 11:14:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzntB-0004Fb-Mq for qemu-devel@nongnu.org; Tue, 02 Jun 2015 11:14:05 -0400 Received: from smtp02.citrix.com ([66.165.176.63]:1526) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzntB-0004FR-I5 for qemu-devel@nongnu.org; Tue, 02 Jun 2015 11:14:01 -0400 From: Stefano Stabellini Date: Tue, 2 Jun 2015 16:10:44 +0100 Message-ID: <1433257845-3690-10-git-send-email-stefano.stabellini@eu.citrix.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 10/11] xen/pt: add a few PCI config space field descriptions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: xen-devel@lists.xensource.com, Jan Beulich , Stefano.Stabellini@eu.citrix.com From: Jan Beulich Since the next patch will turn all not explicitly described fields read-only by default, those fields that have guest writable bits need to be given explicit descriptors. This is a preparatory patch for XSA-131. Signed-off-by: Jan Beulich --- hw/xen/xen_pt_config_init.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index efd8bac..19f926b 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -754,6 +754,15 @@ static XenPTRegInfo xen_pt_emu_reg_vpd[] = { .u.b.write = xen_pt_byte_reg_write, }, { + .offset = PCI_VPD_ADDR, + .size = 2, + .ro_mask = 0x0003, + .emu_mask = 0x0003, + .init = xen_pt_common_reg_init, + .u.w.read = xen_pt_word_reg_read, + .u.w.write = xen_pt_word_reg_write, + }, + { .size = 0, }, }; @@ -889,6 +898,16 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = { .u.w.read = xen_pt_word_reg_read, .u.w.write = xen_pt_word_reg_write, }, + /* Device Status reg */ + { + .offset = PCI_EXP_DEVSTA, + .size = 2, + .res_mask = 0xFFC0, + .ro_mask = 0x0030, + .init = xen_pt_common_reg_init, + .u.w.read = xen_pt_word_reg_read, + .u.w.write = xen_pt_word_reg_write, + }, /* Link Control reg */ { .offset = PCI_EXP_LNKCTL, @@ -900,6 +919,15 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[] = { .u.w.read = xen_pt_word_reg_read, .u.w.write = xen_pt_word_reg_write, }, + /* Link Status reg */ + { + .offset = PCI_EXP_LNKSTA, + .size = 2, + .ro_mask = 0x3FFF, + .init = xen_pt_common_reg_init, + .u.w.read = xen_pt_word_reg_read, + .u.w.write = xen_pt_word_reg_write, + }, /* Device Control 2 reg */ { .offset = 0x28, -- 1.7.10.4