From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzp8Z-0001nM-DK for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:34:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yzp8Y-0000ur-4b for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:33:59 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34364) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzp8X-0000r2-Tt for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:33:58 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Yzp8T-00031V-BA for qemu-devel@nongnu.org; Tue, 02 Jun 2015 17:33:53 +0100 From: Peter Maydell Date: Tue, 2 Jun 2015 17:33:43 +0100 Message-Id: <1433262832-11527-14-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1433262832-11527-1-git-send-email-peter.maydell@linaro.org> References: <1433262832-11527-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 13/22] target-arm: Extend the gic node properties List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Christoffer Dall In preparation for adding the GICv2m which requires address specifiers and is a subnode of the gic, we extend the gic DT definition to specify the #address-cells and #size-cells properties and add an empty ranges property properties of the DT node, since this is required to add the v2m node as a child of the gic node. Note that we must also expand the irq-map to reference the gic with the right address-cells as a consequence of this change. Reviewed-by: Eric Auger Signed-off-by: Christoffer Dall Message-id: 1432897270-7780-4-git-send-email-christoffer.dall@linaro.org Suggested-by: Shanker Donthineni Signed-off-by: Christoffer Dall Signed-off-by: Peter Maydell --- hw/arm/virt.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e5235ef..387dac8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -317,6 +317,9 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi) 2, vbi->memmap[VIRT_GIC_DIST].size, 2, vbi->memmap[VIRT_GIC_CPU].base, 2, vbi->memmap[VIRT_GIC_CPU].size); + qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); + qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); + qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); } @@ -585,7 +588,7 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, int first_irq, const char *nodename) { int devfn, pin; - uint32_t full_irq_map[4 * 4 * 8] = { 0 }; + uint32_t full_irq_map[4 * 4 * 10] = { 0 }; uint32_t *irq_map = full_irq_map; for (devfn = 0; devfn <= 0x18; devfn += 0x8) { @@ -598,13 +601,13 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, uint32_t map[] = { devfn << 8, 0, 0, /* devfn */ pin + 1, /* PCI pin */ - gic_phandle, irq_type, irq_nr, irq_level }; /* GIC irq */ + gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ /* Convert map to big endian */ - for (i = 0; i < 8; i++) { + for (i = 0; i < 10; i++) { irq_map[i] = cpu_to_be32(map[i]); } - irq_map += 8; + irq_map += 10; } } -- 1.9.1