From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzp8b-0001qq-CY for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:34:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yzp8a-0000wr-AA for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:34:01 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34364) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzp8a-0000r2-2r for qemu-devel@nongnu.org; Tue, 02 Jun 2015 12:34:00 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Yzp8S-00030x-WC for qemu-devel@nongnu.org; Tue, 02 Jun 2015 17:33:53 +0100 From: Peter Maydell Date: Tue, 2 Jun 2015 17:33:37 +0100 Message-Id: <1433262832-11527-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1433262832-11527-1-git-send-email-peter.maydell@linaro.org> References: <1433262832-11527-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 07/22] target-arm: Add TLBI_ALLE1{IS} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias Message-id: 1432881807-18164-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 54c7041..5505ba5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2368,6 +2368,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, .access = PL1_W, .type = ARM_CP_NOP }, /* TLBI operations */ + { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbiall_write }, + { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbiall_write }, { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW, -- 1.9.1