[Qemu-devel] [PATCH 0/2] target-arm: Clean up ARMv8 MIDR register space

[Qemu-devel] [PATCH 0/2] target-arm: Clean up ARMv8 MIDR register space

[Sergey Fedorov]

This patch series combines two changes:
 * use correct REVIDR reset value for Cortex-A53/A57
 * add missing MIDR AArch32 aliases

Sergey Fedorov (2):
  target-arm: Fix REVIDR reset value
  target-arm: Add AArch32 MIDR aliases in ARMv8

 target-arm/cpu-qom.h |  1 +
 target-arm/cpu64.c   |  2 ++
 target-arm/helper.c  | 13 ++++++++-----
 3 files changed, 11 insertions(+), 5 deletions(-)

-- 
1.9.1

[Qemu-devel] [PATCH 1/2] target-arm: Fix REVIDR reset value

[Sergey Fedorov]

According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
 target-arm/cpu-qom.h | 1 +
 target-arm/cpu64.c   | 2 ++
 target-arm/helper.c  | 5 ++---
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index ed5a644..c80381d 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -127,6 +127,7 @@ typedef struct ARMCPU {
      * prefix means a constant register.
      */
     uint32_t midr;
+    uint32_t revidr;
     uint32_t reset_fpsid;
     uint32_t mvfr0;
     uint32_t mvfr1;
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index bf7dd68..2fbe99f 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
     cpu->midr = 0x411fd070;
+    cpu->revidr = 0x00000000;
     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
     cpu->mvfr1 = 0x12111111;
@@ -160,6 +161,7 @@ static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     cpu->midr = 0x410fd034;
+    cpu->revidr = 0x00000000;
     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
     cpu->mvfr1 = 0x12111111;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b2b377a..5f8f16d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3355,15 +3355,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
-             * variable-MIDR TI925 behaviour. Instead we have a single
-             * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
+             * variable-MIDR TI925 behaviour.
              */
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
-              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
+              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
             REGINFO_SENTINEL
         };
         ARMCPRegInfo id_cp_reginfo[] = {
-- 
1.9.1

[Qemu-devel] [PATCH 2/2] target-arm: add AArch32 MIDR aliases in ARMv8

[Sergey Fedorov]

According to ARMv8 ARM, there are additional aliases to MIDR system register in
AArch32 state. So add them to the list.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
 target-arm/helper.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5f8f16d..d1998ae 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3354,12 +3354,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             REGINFO_SENTINEL
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
-            /* v8 MIDR -- the wildcard isn't necessary, and nor is the
-             * variable-MIDR TI925 behaviour.
-             */
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
+            /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
+            { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
+              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
+              .access = PL1_R, .resetvalue = cpu->midr },
+            { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
+              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
+              .access = PL1_R, .resetvalue = cpu->midr },
             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
-- 
1.9.1

Re: [Qemu-devel] [PATCH 0/2] target-arm: Clean up ARMv8 MIDR register space

[Peter Maydell]

On 3 June 2015 at 09:44, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
> This patch series combines two changes:
>  * use correct REVIDR reset value for Cortex-A53/A57
>  * add missing MIDR AArch32 aliases
>
> Sergey Fedorov (2):
>   target-arm: Fix REVIDR reset value
>   target-arm: Add AArch32 MIDR aliases in ARMv8
>
>  target-arm/cpu-qom.h |  1 +
>  target-arm/cpu64.c   |  2 ++
>  target-arm/helper.c  | 13 ++++++++-----
>  3 files changed, 11 insertions(+), 5 deletions(-)



Applied to target-arm.next, thanks.

-- PMM