From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z04Hy-0004ov-Jt for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z04Hr-0005NF-Kv for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:42 -0400 Received: from mail-lb0-x22c.google.com ([2a00:1450:4010:c04::22c]:35201) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z04Hr-0005Mi-D2 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:35 -0400 Received: by lbbuc2 with SMTP id uc2so2227278lbb.2 for ; Wed, 03 Jun 2015 01:44:34 -0700 (PDT) From: Sergey Fedorov Date: Wed, 3 Jun 2015 11:44:06 +0300 Message-Id: <1433321048-23793-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH 0/2] target-arm: Clean up ARMv8 MIDR register space List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Sergey Fedorov This patch series combines two changes: * use correct REVIDR reset value for Cortex-A53/A57 * add missing MIDR AArch32 aliases Sergey Fedorov (2): target-arm: Fix REVIDR reset value target-arm: Add AArch32 MIDR aliases in ARMv8 target-arm/cpu-qom.h | 1 + target-arm/cpu64.c | 2 ++ target-arm/helper.c | 13 ++++++++----- 3 files changed, 11 insertions(+), 5 deletions(-) -- 1.9.1