From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z04I1-0004qF-Bh for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z04I0-0005RN-FO for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:45 -0400 Received: from mail-la0-x236.google.com ([2a00:1450:4010:c03::236]:36099) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z04I0-0005Qz-73 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:44 -0400 Received: by laei3 with SMTP id i3so2572565lae.3 for ; Wed, 03 Jun 2015 01:44:43 -0700 (PDT) From: Sergey Fedorov Date: Wed, 3 Jun 2015 11:44:07 +0300 Message-Id: <1433321048-23793-2-git-send-email-serge.fdrv@gmail.com> In-Reply-To: <1433321048-23793-1-git-send-email-serge.fdrv@gmail.com> References: <1433321048-23793-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH 1/2] target-arm: Fix REVIDR reset value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Sergey Fedorov According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57. Signed-off-by: Sergey Fedorov --- target-arm/cpu-qom.h | 1 + target-arm/cpu64.c | 2 ++ target-arm/helper.c | 5 ++--- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index ed5a644..c80381d 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -127,6 +127,7 @@ typedef struct ARMCPU { * prefix means a constant register. */ uint32_t midr; + uint32_t revidr; uint32_t reset_fpsid; uint32_t mvfr0; uint32_t mvfr1; diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bf7dd68..2fbe99f 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; cpu->midr = 0x411fd070; + cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x12111111; @@ -160,6 +161,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->midr = 0x410fd034; + cpu->revidr = 0x00000000; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x12111111; diff --git a/target-arm/helper.c b/target-arm/helper.c index b2b377a..5f8f16d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3355,15 +3355,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; ARMCPRegInfo id_v8_midr_cp_reginfo[] = { /* v8 MIDR -- the wildcard isn't necessary, and nor is the - * variable-MIDR TI925 behaviour. Instead we have a single - * (strictly speaking IMPDEF) alias of the MIDR, REVIDR. + * variable-MIDR TI925 behaviour. */ { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] = { -- 1.9.1