From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z04II-0005B2-7E for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:45:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z04IE-0005Wd-Ai for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:45:02 -0400 Received: from mail-la0-x22b.google.com ([2a00:1450:4010:c03::22b]:32871) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z04IE-0005WS-2t for qemu-devel@nongnu.org; Wed, 03 Jun 2015 04:44:58 -0400 Received: by labpy14 with SMTP id py14so2647051lab.0 for ; Wed, 03 Jun 2015 01:44:57 -0700 (PDT) From: Sergey Fedorov Date: Wed, 3 Jun 2015 11:44:08 +0300 Message-Id: <1433321048-23793-3-git-send-email-serge.fdrv@gmail.com> In-Reply-To: <1433321048-23793-1-git-send-email-serge.fdrv@gmail.com> References: <1433321048-23793-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH 2/2] target-arm: add AArch32 MIDR aliases in ARMv8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Sergey Fedorov According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Signed-off-by: Sergey Fedorov --- target-arm/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5f8f16d..d1998ae 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3354,12 +3354,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) REGINFO_SENTINEL }; ARMCPRegInfo id_v8_midr_cp_reginfo[] = { - /* v8 MIDR -- the wildcard isn't necessary, and nor is the - * variable-MIDR TI925 behaviour. - */ { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, + /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ + { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_R, .resetvalue = cpu->midr }, + { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, + .access = PL1_R, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, -- 1.9.1