From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z052h-0006mZ-D8 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 05:33:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z052e-0007rO-I9 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 05:32:59 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:48566) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z052e-0007rI-De for qemu-devel@nongnu.org; Wed, 03 Jun 2015 05:32:56 -0400 From: Leon Alrae Date: Wed, 3 Jun 2015 10:32:36 +0100 Message-ID: <1433323956-7867-8-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1433323956-7867-1-git-send-email-leon.alrae@imgtec.com> References: <1433323956-7867-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 7/7] target-mips: enable XPA and LPA features List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: james.hogan@imgtec.com, aurelien@aurel32.net Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 05a02eb..836b7bf 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -400,10 +400,11 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_MVH), .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | (1 << CP0C5_CV) | (0 << CP0C5_EVA) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) | @@ -413,11 +414,12 @@ static const mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), .SEGBITS = 32, - .PABITS = 32, + .PABITS = 40, .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, @@ -616,7 +618,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | - (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M), + (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) | + (1U << CP0C3_M), .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1 << CP0C4_M), .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | @@ -628,12 +631,12 @@ static const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x30D8FFFF, .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = 0, + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - .PABITS = 36, + .PABITS = 48, .insn_flags = CPU_MIPS64R6, .mmu_type = MMU_TYPE_R4000, },