From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49820) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0CAO-0007Ae-5d for qemu-devel@nongnu.org; Wed, 03 Jun 2015 13:09:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0CAN-0008Ob-6y for qemu-devel@nongnu.org; Wed, 03 Jun 2015 13:09:24 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36142) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0CAM-0008O0-PR for qemu-devel@nongnu.org; Wed, 03 Jun 2015 13:09:22 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (Postfix) with ESMTPS id 87F0C19CF9D for ; Wed, 3 Jun 2015 17:09:22 +0000 (UTC) From: Paolo Bonzini Date: Wed, 3 Jun 2015 19:08:38 +0200 Message-Id: <1433351328-23326-14-git-send-email-pbonzini@redhat.com> In-Reply-To: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> References: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 13/23] target-i386: create a separate AddressSpace for each CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, kraxel@redhat.com, mst@redhat.com Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Signed-off-by: Paolo Bonzini --- target-i386/cpu-qom.h | 1 + target-i386/cpu.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 31a0c1e..39cd878 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -111,6 +111,7 @@ typedef struct X86CPU { /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; + struct MemoryRegion *cpu_as_root; } X86CPU; static inline X86CPU *x86_env_get_cpu(CPUX86State *env) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 523d0cd..23b57a9 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -44,6 +44,7 @@ #include "hw/qdev-properties.h" #include "hw/cpu/icc_bus.h" #ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" #include "hw/xen/xen.h" #include "hw/i386/apic_internal.h" #endif @@ -2811,6 +2812,18 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #endif mce_init(cpu); + +#ifndef CONFIG_USER_ONLY + if (tcg_enabled()) { + cpu->cpu_as_root = g_new(MemoryRegion, 1); + cs->as = g_new(AddressSpace, 1); + memory_region_init_alias(cpu->cpu_as_root, OBJECT(cpu), "memory", + get_system_memory(), 0, ~0ull); + memory_region_set_enabled(cpu->cpu_as_root, true); + address_space_init(cs->as, cpu->cpu_as_root, "CPU"); + } +#endif + qemu_init_vcpu(cs); /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this @@ -2834,6 +2847,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) cpu_reset(cs); xcc->parent_realize(dev, &local_err); + out: if (local_err != NULL) { error_propagate(errp, local_err); -- 2.4.1