From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49631) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0CA6-0006dP-1W for qemu-devel@nongnu.org; Wed, 03 Jun 2015 13:09:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0CA4-00087n-55 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 13:09:06 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53764) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0CA4-00087W-0g for qemu-devel@nongnu.org; Wed, 03 Jun 2015 13:09:04 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (Postfix) with ESMTPS id C071A8EA46 for ; Wed, 3 Jun 2015 17:09:03 +0000 (UTC) From: Paolo Bonzini Date: Wed, 3 Jun 2015 19:08:30 +0200 Message-Id: <1433351328-23326-6-git-send-email-pbonzini@redhat.com> In-Reply-To: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> References: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 05/23] target-i386: set G=1 in SMM big real mode selectors List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, kraxel@redhat.com, mst@redhat.com Because the limit field's bits 31:20 is 1, G should be 1. VMX actually enforces this, let's do it for completeness in QEMU as well. Signed-off-by: Paolo Bonzini --- target-i386/smm_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 6207c3a..5617a14 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -177,22 +177,22 @@ void do_smm_enter(X86CPU *cpu) cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); } void helper_rsm(CPUX86State *env) -- 2.4.1