From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0GTy-0006kk-Oq for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:45:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0GTo-0003MV-Vy for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:45:54 -0400 From: Alexander Graf Date: Wed, 3 Jun 2015 23:45:31 +0200 Message-Id: <1433367941-119488-31-git-send-email-agraf@suse.de> In-Reply-To: <1433367941-119488-1-git-send-email-agraf@suse.de> References: <1433367941-119488-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 30/40] spapr_pci: create DRConnectors for each PCI slot during PHB realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: peter.maydell@linaro.org, David Gibson , qemu-devel@nongnu.org, Michael Roth From: Michael Roth These will be used to support hotplug/unplug of PCI devices to the PCI bus associated with a particular PHB. We also set up device-tree properties in each PHBs initial FDT to describe the DRCs associated with them. This advertises to guests that each PHB is DR-capable device with physical hotpluggable slots, each managed by the corresponding DRC. This is necessary for allowing hotplugging of devices to it later via bus rescan or guest rpaphp hotplug module. Signed-off-by: Michael Roth Reviewed-by: David Gibson Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- hw/ppc/spapr_pci.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index a2dcc6a..c17e5f2 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -35,6 +35,7 @@ #include "qemu/error-report.h" #include "hw/pci/pci_bus.h" +#include "hw/ppc/spapr_drc.h" /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ #define RTAS_QUERY_FN 0 @@ -880,6 +881,15 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) sphb->lsi_table[i].irq = irq; } + /* allocate connectors for child PCI devices */ + if (sphb->dr_enabled) { + for (i = 0; i < PCI_SLOT_MAX * 8; i++) { + spapr_dr_connector_new(OBJECT(phb), + SPAPR_DR_CONNECTOR_TYPE_PCI, + (sphb->index << 16) | i); + } + } + if (!info->finish_realize) { error_setg(errp, "finish_realize not defined"); return; @@ -1096,7 +1106,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt) { - int bus_off, i, j; + int bus_off, i, j, ret; char nodename[256]; uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; const uint64_t mmiosize = memory_region_size(&phb->memwindow); @@ -1188,6 +1198,12 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, tcet->liobn, tcet->bus_offset, tcet->nb_table << tcet->page_shift); + ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb), + SPAPR_DR_CONNECTOR_TYPE_PCI); + if (ret) { + return ret; + } + return 0; } -- 1.8.1.4