From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0jD5-0003J2-3c for qemu-devel@nongnu.org; Fri, 05 Jun 2015 00:26:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0jD2-0004qs-0r for qemu-devel@nongnu.org; Fri, 05 Jun 2015 00:26:22 -0400 Received: from e28smtp09.in.ibm.com ([122.248.162.9]:33378) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0jD1-0004o5-CE for qemu-devel@nongnu.org; Fri, 05 Jun 2015 00:26:19 -0400 Received: from /spool/local by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 5 Jun 2015 09:56:14 +0530 From: Bharata B Rao Date: Fri, 5 Jun 2015 09:55:50 +0530 Message-Id: <1433478358-993-1-git-send-email-bharata@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 0/8] sPAPR CPU hotplug pre-requisites List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: thuth@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, tyreld@linux.vnet.ibm.com, Bharata B Rao , nfont@linux.vnet.ibm.com, david@gibson.dropbear.id.au Hi, These are the patches that are required to support CPU hotplug for sPAPR guests. Until now these patches were carried as part of the combined patchset for sPAPR CPU and Memory hotplug. Since some of these patches are well reviewed and can be included before the core hotplug changes, I am posting them as a separate series. The last post of these patches were with the combined series version 3. https://lists.nongnu.org/archive/html/qemu-devel/2015-04/msg02910.html This split-out series starts with v4 which has the following minor changes: - Using maxram_size from MachineState instead of sPAPREnvironment. (2/8) - Added a patch to walk CPUs list in reverse order. (3/8) - Walking CPUs list in reverse order to ensure CPU device tree entries are filled up in proper order in device tree. (4/8) - Use of MSR_EP define instead of using direct number. (5/8) - Don't set irq for those CPUs that are already removed during XICS reset. (8/8) - Removed David Gibson's SoB from some patches as there were some minor changes in them. This series applies against spapr-next branch of David Gibson's tree. Bharata B Rao (8): spapr: Consider max_cpus during xics initialization spapr: Support ibm,lrdr-capacity device tree property cpus: Add a macro to walk CPUs in reverse spapr: Reorganize CPU dt generation code spapr: Consolidate cpu init code into a routine ppc: Update cpu_model in MachineState xics_kvm: Don't enable KVM_CAP_IRQ_XICS if already enabled xics_kvm: Add cpu_destroy method to XICS docs/specs/ppc-spapr-hotplug.txt | 18 ++ hw/intc/xics.c | 14 ++ hw/intc/xics_kvm.c | 25 ++- hw/ppc/mac_newworld.c | 10 +- hw/ppc/mac_oldworld.c | 7 +- hw/ppc/ppc440_bamboo.c | 7 +- hw/ppc/prep.c | 7 +- hw/ppc/spapr.c | 352 +++++++++++++++++++++------------------ hw/ppc/spapr_rtas.c | 16 ++ hw/ppc/virtex_ml507.c | 7 +- include/hw/ppc/spapr.h | 2 + include/hw/ppc/xics.h | 3 + include/qom/cpu.h | 2 + 13 files changed, 289 insertions(+), 181 deletions(-) -- 2.1.0