From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0tNH-00046j-HA for qemu-devel@nongnu.org; Fri, 05 Jun 2015 11:17:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0tNG-0000MA-6D for qemu-devel@nongnu.org; Fri, 05 Jun 2015 11:17:35 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47222) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0tNG-0000M1-1n for qemu-devel@nongnu.org; Fri, 05 Jun 2015 11:17:34 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id BD0D32CAB34 for ; Fri, 5 Jun 2015 15:17:33 +0000 (UTC) Received: from donizetti.redhat.com (ovpn-112-29.ams2.redhat.com [10.36.112.29]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t55FG4l2012808 for ; Fri, 5 Jun 2015 11:17:32 -0400 From: Paolo Bonzini Date: Fri, 5 Jun 2015 17:15:51 +0200 Message-Id: <1433517363-32335-51-git-send-email-pbonzini@redhat.com> In-Reply-To: <1433517363-32335-1-git-send-email-pbonzini@redhat.com> References: <1433517363-32335-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 50/62] target-i386: create a separate AddressSpace for each CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Signed-off-by: Paolo Bonzini --- target-i386/cpu-qom.h | 1 + target-i386/cpu.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 31a0c1e..39cd878 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -111,6 +111,7 @@ typedef struct X86CPU { /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; + struct MemoryRegion *cpu_as_root; } X86CPU; static inline X86CPU *x86_env_get_cpu(CPUX86State *env) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0faca03..051abc9 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -44,6 +44,7 @@ #include "hw/qdev-properties.h" #include "hw/cpu/icc_bus.h" #ifndef CONFIG_USER_ONLY +#include "exec/address-spaces.h" #include "hw/xen/xen.h" #include "hw/i386/apic_internal.h" #endif @@ -2811,6 +2812,18 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #endif mce_init(cpu); + +#ifndef CONFIG_USER_ONLY + if (tcg_enabled()) { + cpu->cpu_as_root = g_new(MemoryRegion, 1); + cs->as = g_new(AddressSpace, 1); + memory_region_init_alias(cpu->cpu_as_root, OBJECT(cpu), "memory", + get_system_memory(), 0, ~0ull); + memory_region_set_enabled(cpu->cpu_as_root, true); + address_space_init(cs->as, cpu->cpu_as_root, "CPU"); + } +#endif + qemu_init_vcpu(cs); /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this @@ -2834,6 +2847,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) cpu_reset(cs); xcc->parent_realize(dev, &local_err); + out: if (local_err != NULL) { error_propagate(errp, local_err); -- 2.4.1