From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z27Du-0003rQ-Pv for qemu-devel@nongnu.org; Mon, 08 Jun 2015 20:16:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z27Dr-0005BL-Uy for qemu-devel@nongnu.org; Mon, 08 Jun 2015 20:16:58 -0400 Received: from mail-qc0-x236.google.com ([2607:f8b0:400d:c01::236]:34622) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z27Dr-0005B7-R2 for qemu-devel@nongnu.org; Mon, 08 Jun 2015 20:16:55 -0400 Received: by qcej9 with SMTP id j9so1105174qce.1 for ; Mon, 08 Jun 2015 17:16:55 -0700 (PDT) From: Paulo Alcantara Date: Mon, 8 Jun 2015 21:16:14 -0300 Message-Id: <1433808974-28459-2-git-send-email-pcacjr@zytor.com> In-Reply-To: <1433808974-28459-1-git-send-email-pcacjr@zytor.com> References: <1433808974-28459-1-git-send-email-pcacjr@zytor.com> Subject: [Qemu-devel] [PATCH v5 2/2] OvmfPkg/PlatformPei: Initialise RCBA (B0:D31:F0 0xf0) register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: edk2-devel@lists.sourceforge.net Cc: mst@redhat.com, jordan.l.justen@intel.com, qemu-devel@nongnu.org, Paulo Alcantara , pbonzini@redhat.com, lersek@redhat.com This patch initialises root complex register block BAR in order to support TCO watchdog emulation features (e.g. reboot upon NO_REBOOT bit not set) on QEMU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paulo Alcantara --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 5 +++++ OvmfPkg/PlatformPei/Platform.c | 17 ++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 4f59a7c..18b34a3 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -77,6 +77,9 @@ #define ICH9_GEN_PMCON_1 0xA0 #define ICH9_GEN_PMCON_1_SMI_LOCK BIT4 +#define ICH9_RCBA 0xF0 +#define ICH9_RCBA_EN BIT0 + // // IO ports // @@ -90,4 +93,6 @@ #define ICH9_SMI_EN_APMC_EN BIT5 #define ICH9_SMI_EN_GBL_SMI_EN BIT0 +#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000 + #endif diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 0e41d30..1ad5bfc 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -214,13 +214,18 @@ MemMapInitialization ( // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB // 0xFED00000 HPET 1 KB - // 0xFED00400 gap 1023 KB + // 0xFED00400 gap 111 KB + // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB + // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ? BASE_2GB : TopOfLowRam, 0xFC000000); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + } AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } } @@ -292,6 +297,16 @@ MiscInitialization ( // PciOr8 (AcpiCtlReg, AcpiEnBit); } + + if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + // + // Set Root Complex Register Block BAR + // + PciWrite32 ( + POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), + ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN + ); + } } -- 2.1.0