From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2McH-0005sk-B9 for qemu-devel@nongnu.org; Tue, 09 Jun 2015 12:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z2McC-0004eb-LC for qemu-devel@nongnu.org; Tue, 09 Jun 2015 12:43:08 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:23543) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2McC-0004eD-97 for qemu-devel@nongnu.org; Tue, 09 Jun 2015 12:43:04 -0400 From: Leon Alrae Date: Tue, 9 Jun 2015 17:42:33 +0100 Message-ID: <1433868154-20384-7-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1433868154-20384-1-git-send-email-leon.alrae@imgtec.com> References: <1433868154-20384-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v3 6/7] target-mips: remove misleading comments in translate_init.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: james.hogan@imgtec.com, aurelien@aurel32.net PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is the architectural limit) in QEMU. Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 00369f1..05a02eb 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -553,9 +553,6 @@ static const mips_def_t mips_defs[] = (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - /* The architectural limit is 59, but we have hardcoded 36 bit - in some places... - .PABITS = 59, */ /* the architectural limit */ .PABITS = 36, .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, .mmu_type = MMU_TYPE_R4000, @@ -636,9 +633,6 @@ static const mips_def_t mips_defs[] = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - /* The architectural limit is 59, but we have hardcoded 36 bit - in some places... - .PABITS = 59, */ /* the architectural limit */ .PABITS = 36, .insn_flags = CPU_MIPS64R6, .mmu_type = MMU_TYPE_R4000, @@ -702,9 +696,6 @@ static const mips_def_t mips_defs[] = (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, - /* The architectural limit is 59, but we have hardcoded 36 bit - in some places... - .PABITS = 59, */ /* the architectural limit */ .PABITS = 36, .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, .mmu_type = MMU_TYPE_R4000,