From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44792) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2QpE-0006DV-NR for qemu-devel@nongnu.org; Tue, 09 Jun 2015 17:12:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z2QpD-0003fB-Pi for qemu-devel@nongnu.org; Tue, 09 Jun 2015 17:12:48 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:34730) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z2QpD-0003ep-Jk for qemu-devel@nongnu.org; Tue, 09 Jun 2015 17:12:47 -0400 Received: by payr10 with SMTP id r10so20576469pay.1 for ; Tue, 09 Jun 2015 14:12:47 -0700 (PDT) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id rx6sm6474783pbc.62.2015.06.09.14.12.44 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Jun 2015 14:12:45 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 9 Jun 2015 14:12:34 -0700 Message-Id: <1433884354-2550-5-git-send-email-rth@twiddle.net> In-Reply-To: <1433884354-2550-1-git-send-email-rth@twiddle.net> References: <1433884354-2550-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 3/3] target-alpha: Inline hw_ret List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/helper.h | 2 -- target-alpha/sys_helper.c | 8 -------- target-alpha/translate.c | 15 ++++++++++----- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index e7f0450..42bb247 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -91,8 +91,6 @@ DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64) #if !defined (CONFIG_USER_ONLY) -DEF_HELPER_2(hw_ret, void, env, i64) - DEF_HELPER_2(ldl_phys, i64, env, i64) DEF_HELPER_2(ldq_phys, i64, env, i64) DEF_HELPER_2(ldl_l_phys, i64, env, i64) diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c index 211991d..22e5b08 100644 --- a/target-alpha/sys_helper.c +++ b/target-alpha/sys_helper.c @@ -40,14 +40,6 @@ uint64_t helper_load_pcc(CPUAlphaState *env) /* PALcode support special instructions */ #ifndef CONFIG_USER_ONLY -void helper_hw_ret(CPUAlphaState *env, uint64_t a) -{ - env->pc = a & ~3; - env->intr_flag = 0; - env->lock_addr = -1; - env->pal_mode = a & 1; -} - void helper_tbia(CPUAlphaState *env) { tlb_flush(CPU(alpha_env_get_cpu(env)), 1); diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 04c42fc..82d492b 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2635,13 +2635,18 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return address from EXC_ADDR. This turns out to be useful for our emulation PALcode, so continue to accept it. */ - tmp = tcg_temp_new(); - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); - gen_helper_hw_ret(cpu_env, tmp); - tcg_temp_free(tmp); + ctx->lit = vb = tcg_temp_new(); + tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr)); } else { - gen_helper_hw_ret(cpu_env, load_gpr(ctx, rb)); + vb = load_gpr(ctx, rb); } + tmp = tcg_temp_new(); + tcg_gen_movi_i64(tmp, 0); + tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); + tcg_gen_movi_i64(cpu_lock_addr, -1); + tcg_gen_andi_i64(tmp, vb, 1); + tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode)); + tcg_gen_andi_i64(cpu_pc, vb, ~3); ret = EXIT_PC_UPDATED; break; #else -- 2.1.0