From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3LNy-00058y-FM for qemu-devel@nongnu.org; Fri, 12 Jun 2015 05:36:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3LNu-0006Y4-54 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 05:36:26 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:2712) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3LNt-0006XI-RB for qemu-devel@nongnu.org; Fri, 12 Jun 2015 05:36:21 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 2AA95EF341F2B for ; Fri, 12 Jun 2015 10:36:19 +0100 (IST) From: Leon Alrae Date: Fri, 12 Jun 2015 10:35:12 +0100 Message-ID: <1434101736-11558-6-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1434101736-11558-1-git-send-email-leon.alrae@imgtec.com> References: <1434101736-11558-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PULL 05/29] softmmu: Add probe_write() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Yongbok Kim From: Yongbok Kim Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Signed-off-by: Yongbok Kim Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- include/exec/exec-all.h | 2 ++ softmmu_template.h | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2f7a4f1..2573e8c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -105,6 +105,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, + uintptr_t retaddr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { diff --git a/softmmu_template.h b/softmmu_template.h index 39f571b..d42d89d 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -548,6 +548,28 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, helper_te_st_name(env, addr, val, oi, GETRA()); } +#if DATA_SIZE == 1 +/* Probe for whether the specified guest write access is permitted. + * If it is not permitted then an exception will be taken in the same + * way as if this were a real write access (and we will not return). + * Otherwise the function will return, and there will be a valid + * entry in the TLB for this access. + */ +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, + uintptr_t retaddr) +{ + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + /* TLB entry is for a different page */ + if (!VICTIM_TLB_HIT(addr_write)) { + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); + } + } +} +#endif #endif /* !defined(SOFTMMU_CODE_ACCESS) */ #undef READ_ACCESS_TYPE -- 2.1.0