From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8I-0007ix-Jc for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4Y8G-0001Vy-Qz for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:14 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8G-0001AA-GY for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:12 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z4Y82-0003Vz-PH for qemu-devel@nongnu.org; Mon, 15 Jun 2015 18:24:58 +0100 From: Peter Maydell Date: Mon, 15 Jun 2015 18:24:39 +0100 Message-Id: <1434389098-13430-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> References: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 09/28] target-arm: add AArch32 MIDR aliases in ARMv8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Sergey Fedorov According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Signed-off-by: Sergey Fedorov Message-id: 1433321048-23793-3-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 8053ad5..16195b3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3423,12 +3423,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) REGINFO_SENTINEL }; ARMCPRegInfo id_v8_midr_cp_reginfo[] = { - /* v8 MIDR -- the wildcard isn't necessary, and nor is the - * variable-MIDR TI925 behaviour. - */ { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr }, + /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ + { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, + .access = PL1_R, .resetvalue = cpu->midr }, + { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, + .access = PL1_R, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, -- 1.9.1