From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 16/28] hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps
Date: Mon, 15 Jun 2015 18:24:46 +0100 [thread overview]
Message-ID: <1434389098-13430-17-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org>
Update the pxa2xx_mmci device to stop using the old_mmio read
and write callbacks in its MemoryRegionOps. This actually
simplifies the code because the separate byte/halfword/word
access functions were all calling into a single function to
do the work anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1434117989-7367-6-git-send-email-peter.maydell@linaro.org
---
hw/sd/pxa2xx_mmci.c | 68 +++++++----------------------------------------------
1 file changed, 8 insertions(+), 60 deletions(-)
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
index ac3ab39..d1fe6d5 100644
--- a/hw/sd/pxa2xx_mmci.c
+++ b/hw/sd/pxa2xx_mmci.c
@@ -48,7 +48,6 @@ struct PXA2xxMMCIState {
int resp_len;
int cmdreq;
- int ac_width;
};
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
@@ -215,7 +214,7 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
pxa2xx_mmci_fifo_update(s);
}
-static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
+static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret;
@@ -257,8 +256,8 @@ static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
return 0;
case MMC_RXFIFO:
ret = 0;
- while (s->ac_width -- && s->rx_len) {
- ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
+ while (size-- && s->rx_len) {
+ ret |= s->rx_fifo[s->rx_start++] << (size << 3);
s->rx_start &= 0x1f;
s->rx_len --;
}
@@ -277,7 +276,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
}
static void pxa2xx_mmci_write(void *opaque,
- hwaddr offset, uint32_t value)
+ hwaddr offset, uint64_t value, unsigned size)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
@@ -370,9 +369,9 @@ static void pxa2xx_mmci_write(void *opaque,
break;
case MMC_TXFIFO:
- while (s->ac_width -- && s->tx_len < 0x20)
+ while (size-- && s->tx_len < 0x20)
s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
- (value >> (s->ac_width << 3)) & 0xff;
+ (value >> (size << 3)) & 0xff;
s->intreq &= ~INT_TXFIFO_REQ;
pxa2xx_mmci_fifo_update(s);
break;
@@ -386,60 +385,9 @@ static void pxa2xx_mmci_write(void *opaque,
}
}
-static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset)
-{
- PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
- s->ac_width = 1;
- return pxa2xx_mmci_read(opaque, offset);
-}
-
-static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset)
-{
- PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
- s->ac_width = 2;
- return pxa2xx_mmci_read(opaque, offset);
-}
-
-static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset)
-{
- PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
- s->ac_width = 4;
- return pxa2xx_mmci_read(opaque, offset);
-}
-
-static void pxa2xx_mmci_writeb(void *opaque,
- hwaddr offset, uint32_t value)
-{
- PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
- s->ac_width = 1;
- pxa2xx_mmci_write(opaque, offset, value);
-}
-
-static void pxa2xx_mmci_writeh(void *opaque,
- hwaddr offset, uint32_t value)
-{
- PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
- s->ac_width = 2;
- pxa2xx_mmci_write(opaque, offset, value);
-}
-
-static void pxa2xx_mmci_writew(void *opaque,
- hwaddr offset, uint32_t value)
-{
- PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
- s->ac_width = 4;
- pxa2xx_mmci_write(opaque, offset, value);
-}
-
static const MemoryRegionOps pxa2xx_mmci_ops = {
- .old_mmio = {
- .read = { pxa2xx_mmci_readb,
- pxa2xx_mmci_readh,
- pxa2xx_mmci_readw, },
- .write = { pxa2xx_mmci_writeb,
- pxa2xx_mmci_writeh,
- pxa2xx_mmci_writew, },
- },
+ .read = pxa2xx_mmci_read,
+ .write = pxa2xx_mmci_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
--
1.9.1
next prev parent reply other threads:[~2015-06-15 17:25 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-15 17:24 [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 01/28] target-arm: Handle "extended small page" descriptors correctly Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 02/28] target-arm: use extended address bits from supersection short descriptor Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 03/28] arm_gic: gic_update should always update all cores Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 04/28] hw/display/exynos4210_fimd: Fix bit-swapping code Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 05/28] target-arm/cpu.h: remove pending_exception Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 06/28] target-arm/kvm64: Add cortex-a53 cpu support Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 07/28] hw/arm/virt: Add cortex-a53 cpu support in machine virt Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 08/28] target-arm: Fix REVIDR reset value Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 09/28] target-arm: add AArch32 MIDR aliases in ARMv8 Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 10/28] MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 11/28] target-arm: Use the kernel's idea of MPIDR if we're using KVM Peter Maydell
2015-06-16 12:02 ` Pavel Fedin
2015-06-16 12:12 ` Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 12/28] hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 13/28] hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMState Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 14/28] hw/arm/pxa2xx: Add reset method for pxa2xx_ssp Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 15/28] hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState Peter Maydell
2015-06-15 17:24 ` Peter Maydell [this message]
2015-06-15 17:24 ` [Qemu-devel] [PULL 17/28] target-arm: Add the THUMB_DSP feature Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 18/28] arm: Do not define TLBTR in PMSA systems Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 19/28] arm: Don't add v7mp registers in MPU systems Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 20/28] arm: helper: Factor out CP regs common to [pv]msa Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 21/28] arm: Refactor get_phys_addr FSR return mechanism Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 22/28] arm: Implement uniprocessor with MP config Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 23/28] arm: Add has-mpu property Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 24/28] arm: helper: rename get_phys_addr_mpu Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 25/28] hw/arm/boot: fix rom_reset notifier registration order Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 27/28] ACPI: Add definitions for the SPCR table Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 28/28] hw/arm/virt-acpi-build: Add " Peter Maydell
2015-06-16 8:06 ` [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell
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