From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60757) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8E-0007Yx-7S for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4Y8C-0001Qn-71 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:10 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8C-0001AA-1K for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:08 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z4Y83-0003X2-JB for qemu-devel@nongnu.org; Mon, 15 Jun 2015 18:24:59 +0100 From: Peter Maydell Date: Mon, 15 Jun 2015 18:24:52 +0100 Message-Id: <1434389098-13430-23-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> References: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 22/28] arm: Implement uniprocessor with MP config List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Peter Crosthwaite Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Signed-off-by: Peter Crosthwaite Message-id: a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 3 +++ target-arm/helper.c | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 24a4cfb..57b4a12 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -116,6 +116,9 @@ typedef struct ARMCPU { /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; + /* Uniprocessor system with MP extensions */ + bool mp_is_up; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target-arm/helper.c b/target-arm/helper.c index f51dece..f038a03a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2075,9 +2075,11 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) mpidr |= (1U << 31); /* Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set - * bit 30. (For instance, A9UP.) However we do - * not currently model any of those cores. + * bit 30. (For instance, Cortex-R5). */ + if (cpu->mp_is_up) { + mpidr |= (1u << 30); + } } return mpidr; } -- 1.9.1