From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y8B-0007TM-Ed for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4Y89-0001Ko-Gl for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:07 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4Y89-0001AA-BF for qemu-devel@nongnu.org; Mon, 15 Jun 2015 13:25:05 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z4Y82-0003VP-E2 for qemu-devel@nongnu.org; Mon, 15 Jun 2015 18:24:58 +0100 From: Peter Maydell Date: Mon, 15 Jun 2015 18:24:33 +0100 Message-Id: <1434389098-13430-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> References: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 03/28] arm_gic: gic_update should always update all cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Johan Karlsson This patch fixes so that gic_update always updates all the cores with new pending irq states. If the function returns early it is possible to get interrupts that has already been acknowledged. Signed-off-by: Johan Karlsson [PMM: rebased to apply to current master] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index c1d2e70..454bfd7 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -71,7 +71,7 @@ void gic_update(GICState *s) || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) { qemu_irq_lower(s->parent_irq[cpu]); qemu_irq_lower(s->parent_fiq[cpu]); - return; + continue; } best_prio = 0x100; best_irq = 1023; -- 1.9.1