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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 06/28] target-arm/kvm64: Add cortex-a53 cpu support
Date: Mon, 15 Jun 2015 18:24:36 +0100	[thread overview]
Message-ID: <1434389098-13430-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1434389098-13430-1-git-send-email-peter.maydell@linaro.org>

From: Shannon Zhao <shannon.zhao@linaro.org>

Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has
added Cortex-A53 cpu support for target-arm, this patch just enables it
for kvm-arm.

Here adding XGENE_POTENZA just makes the enum continuous.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1433207452-4512-2-git-send-email-shannon.zhao@linaro.org
[PMM: Don't add the CPU types to cpus_to_try[]; this array only
 lists old CPUs which were supported in pre-PREFERRED_TARGET kernels]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu64.c      | 1 +
 target-arm/kvm-consts.h | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index bf7dd68..dd6f9d8 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -159,6 +159,7 @@ static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
     set_feature(&cpu->env, ARM_FEATURE_CRC);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
     cpu->midr = 0x410fd034;
     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h
index aea12f1..943bf89 100644
--- a/target-arm/kvm-consts.h
+++ b/target-arm/kvm-consts.h
@@ -127,6 +127,8 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED)
 #define QEMU_KVM_ARM_TARGET_AEM_V8 0
 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
+#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
+#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
 
 /* There's no kernel define for this: sentinel value which
  * matches no KVM target value for either 64 or 32 bit
@@ -137,6 +139,8 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53)
 #else
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15)
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7)
-- 
1.9.1

  parent reply	other threads:[~2015-06-15 17:25 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-15 17:24 [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 01/28] target-arm: Handle "extended small page" descriptors correctly Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 02/28] target-arm: use extended address bits from supersection short descriptor Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 03/28] arm_gic: gic_update should always update all cores Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 04/28] hw/display/exynos4210_fimd: Fix bit-swapping code Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 05/28] target-arm/cpu.h: remove pending_exception Peter Maydell
2015-06-15 17:24 ` Peter Maydell [this message]
2015-06-15 17:24 ` [Qemu-devel] [PULL 07/28] hw/arm/virt: Add cortex-a53 cpu support in machine virt Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 08/28] target-arm: Fix REVIDR reset value Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 09/28] target-arm: add AArch32 MIDR aliases in ARMv8 Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 10/28] MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 11/28] target-arm: Use the kernel's idea of MPIDR if we're using KVM Peter Maydell
2015-06-16 12:02   ` Pavel Fedin
2015-06-16 12:12     ` Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 12/28] hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 13/28] hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMState Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 14/28] hw/arm/pxa2xx: Add reset method for pxa2xx_ssp Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 15/28] hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 16/28] hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 17/28] target-arm: Add the THUMB_DSP feature Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 18/28] arm: Do not define TLBTR in PMSA systems Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 19/28] arm: Don't add v7mp registers in MPU systems Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 20/28] arm: helper: Factor out CP regs common to [pv]msa Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 21/28] arm: Refactor get_phys_addr FSR return mechanism Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 22/28] arm: Implement uniprocessor with MP config Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 23/28] arm: Add has-mpu property Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 24/28] arm: helper: rename get_phys_addr_mpu Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 25/28] hw/arm/boot: fix rom_reset notifier registration order Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 26/28] target-arm: Correct "preferred return address" for cpreg access exceptions Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 27/28] ACPI: Add definitions for the SPCR table Peter Maydell
2015-06-15 17:24 ` [Qemu-devel] [PULL 28/28] hw/arm/virt-acpi-build: Add " Peter Maydell
2015-06-16  8:06 ` [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell

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