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From: John Snow <jsnow@redhat.com>
To: qemu-block@nongnu.org
Cc: kwolf@redhat.com, John Snow <jsnow@redhat.com>,
	qemu-devel@nongnu.org, stefanha@redhat.com
Subject: [Qemu-devel] [PATCH 1/4] ahci: Do not ignore memory access read size
Date: Mon, 15 Jun 2015 18:22:42 -0400	[thread overview]
Message-ID: <1434406965-30883-2-git-send-email-jsnow@redhat.com> (raw)
In-Reply-To: <1434406965-30883-1-git-send-email-jsnow@redhat.com>

The only guidance the AHCI specification gives on memory access is:
"Register accesses shall have a maximum size of 64-bits; 64-bit access
must not cross an 8-byte alignment boundary."

In practice, a real Q35/ICH9 responds to 1, 2, 4 and 8 byte reads
regardless of alignment. Windows 7 can also be observed making 1 byte
reads to the middle of 32 bit registers.

Introduce a wrapper to supper unaligned accesses to AHCI.
This wrapper will support aligned 8 byte reads, but will make
no effort to support unaligned 8 byte reads, which although they
will work on real hardware, are not guaranteed to work and do
not appear to be used by either Windows or Linux.

Signed-off-by: John Snow <jsnow@redhat.com>
---
 hw/ide/ahci.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 9e5d862..55779fb 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -331,8 +331,7 @@ static void  ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
     }
 }
 
-static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
 {
     AHCIState *s = opaque;
     uint32_t val = 0;
@@ -368,6 +367,24 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
 }
 
 
+static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+    hwaddr aligned = addr & ~0x3;
+    int ofst = addr - aligned;
+    uint64_t lo = ahci_mem_read_32(opaque, aligned);
+    uint64_t hi;
+
+    /* if 1/2/4 byte read does not cross 4 byte boundary */
+    if (ofst + size <= 4) {
+        return lo >> (ofst * 8);
+    }
+
+    /* If the 64bit read is unaligned, we will produce undefined
+     * results. AHCI does not support unaligned 64bit reads. */
+    hi = ahci_mem_read_32(opaque, aligned + 4);
+    return (hi << 32) | lo;
+}
+
 
 static void ahci_mem_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned size)
-- 
2.1.0

  reply	other threads:[~2015-06-15 22:22 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-15 22:22 [Qemu-devel] [PATCH 0/4] ahci: misc fixes/tests for 2.4 John Snow
2015-06-15 22:22 ` John Snow [this message]
2015-06-15 22:55   ` [Qemu-devel] [PATCH 1/4] ahci: Do not ignore memory access read size Eric Blake
2015-06-15 23:09     ` John Snow
2015-06-15 23:28       ` Eric Blake
2015-06-15 23:44         ` John Snow
2015-06-16  4:04           ` Eric Blake
2015-06-15 22:22 ` [Qemu-devel] [PATCH 2/4] qtest/ahci: add test_max John Snow
2015-06-15 22:22 ` [Qemu-devel] [PATCH 3/4] libqos/ahci: fix memory management bugs John Snow
2015-06-15 22:22 ` [Qemu-devel] [PATCH 4/4] qtest/ahci: add port_reset test John Snow

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