From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: lersek@redhat.com, mst@redhat.com
Subject: [Qemu-devel] [PATCH 02/12] target-i386: add support for SMBASE MSR and SMIs
Date: Thu, 18 Jun 2015 18:28:42 +0200 [thread overview]
Message-ID: <1434644932-90017-2-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1434644648-89776-1-git-send-email-pbonzini@redhat.com>
Apart from the MSR, the smi field of struct kvm_vcpu_events has to be
translated into the corresponding CPUX86State fields. Also,
memory transaction flags depend on SMM state, so pull it from struct
kvm_run on every exit from KVM to userspace.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-i386/cpu.h | 1 +
target-i386/kvm.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
2 files changed, 90 insertions(+), 9 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 603aaf0..ac39291 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -314,6 +314,7 @@
#define MSR_P6_PERFCTR0 0xc1
+#define MSR_IA32_SMBASE 0x9e
#define MSR_MTRRcap 0xfe
#define MSR_MTRRcap_VCNT 8
#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 5a236e3..6ee5feb 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -74,6 +74,7 @@ static bool has_msr_feature_control;
static bool has_msr_async_pf_en;
static bool has_msr_pv_eoi_en;
static bool has_msr_misc_enable;
+static bool has_msr_smbase;
static bool has_msr_bndcfgs;
static bool has_msr_kvm_steal_time;
static int lm_capable_kernel;
@@ -820,6 +821,10 @@ static int kvm_get_supported_msrs(KVMState *s)
has_msr_tsc_deadline = true;
continue;
}
+ if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
+ has_msr_smbase = true;
+ continue;
+ }
if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
has_msr_misc_enable = true;
continue;
@@ -1246,6 +1251,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
env->msr_ia32_misc_enable);
}
+ if (has_msr_smbase) {
+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
+ }
if (has_msr_bndcfgs) {
kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
}
@@ -1607,6 +1615,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_misc_enable) {
msrs[n++].index = MSR_IA32_MISC_ENABLE;
}
+ if (has_msr_smbase) {
+ msrs[n++].index = MSR_IA32_SMBASE;
+ }
if (has_msr_feature_control) {
msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
}
@@ -1761,6 +1772,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_MISC_ENABLE:
env->msr_ia32_misc_enable = msrs[i].data;
break;
+ case MSR_IA32_SMBASE:
+ env->smbase = msrs[i].data;
+ break;
case MSR_IA32_FEATURE_CONTROL:
env->msr_ia32_feature_control = msrs[i].data;
break;
@@ -1924,6 +1938,7 @@ static int kvm_put_apic(X86CPU *cpu)
static int kvm_put_vcpu_events(X86CPU *cpu, int level)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
struct kvm_vcpu_events events = {};
@@ -1948,6 +1963,24 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level)
events.sipi_vector = env->sipi_vector;
+ if (has_msr_smbase) {
+ events.smi.smm = !!(env->hflags & HF_SMM_MASK);
+ events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
+ if (kvm_irqchip_in_kernel()) {
+ /* As soon as these are moved to the kernel, remove them
+ * from cs->interrupt_request.
+ */
+ events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
+ events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
+ cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
+ } else {
+ /* Keep these in cs->interrupt_request. */
+ events.smi.pending = 0;
+ events.smi.latched_init = 0;
+ }
+ events.flags |= KVM_VCPUEVENT_VALID_SMM;
+ }
+
events.flags = 0;
if (level >= KVM_PUT_RESET_STATE) {
events.flags |=
@@ -1967,6 +2000,7 @@ static int kvm_get_vcpu_events(X86CPU *cpu)
return 0;
}
+ memset(&events, 0, sizeof(events));
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
if (ret < 0) {
return ret;
@@ -1988,6 +2022,29 @@ static int kvm_get_vcpu_events(X86CPU *cpu)
env->hflags2 &= ~HF2_NMI_MASK;
}
+ if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
+ if (events.smi.smm) {
+ env->hflags |= HF_SMM_MASK;
+ } else {
+ env->hflags &= ~HF_SMM_MASK;
+ }
+ if (events.smi.pending) {
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
+ } else {
+ cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
+ }
+ if (events.smi.smm_inside_nmi) {
+ env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
+ } else {
+ env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
+ }
+ if (events.smi.latched_init) {
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
+ } else {
+ cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
+ }
+ }
+
env->sipi_vector = events.sipi_vector;
return 0;
@@ -2191,13 +2248,24 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
int ret;
/* Inject NMI */
- if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
- cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
- DPRINTF("injected NMI\n");
- ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
- if (ret < 0) {
- fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
- strerror(-ret));
+ if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
+ if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
+ cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ DPRINTF("injected NMI\n");
+ ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
+ if (ret < 0) {
+ fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
+ strerror(-ret));
+ }
+ }
+ if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
+ cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
+ DPRINTF("injected SMI\n");
+ ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
+ if (ret < 0) {
+ fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
+ strerror(-ret));
+ }
}
}
@@ -2206,7 +2274,13 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
* pending TPR access reports.
*/
if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
- cpu->exit_request = 1;
+ if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
+ !(env->hflags & HF_SMM_MASK)) {
+ cpu->exit_request = 1;
+ }
+ if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
+ cpu->exit_request = 1;
+ }
}
if (!kvm_irqchip_in_kernel()) {
@@ -2252,6 +2326,11 @@ MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
+ if (run->flags & KVM_RUN_X86_SMM) {
+ env->hflags |= HF_SMM_MASK;
+ } else {
+ env->hflags &= HF_SMM_MASK;
+ }
if (run->if_flag) {
env->eflags |= IF_MASK;
} else {
@@ -2290,7 +2369,8 @@ int kvm_arch_process_async_events(CPUState *cs)
}
}
- if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
+ if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
+ !(env->hflags & HF_SMM_MASK)) {
kvm_cpu_synchronize_state(cs);
do_cpu_init(cpu);
}
--
1.8.3.1
next prev parent reply other threads:[~2015-06-18 16:29 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-18 16:23 [Qemu-devel] [PATCH for-2.4 00/12] pc: KVM support for SMRAM Paolo Bonzini
2015-06-18 16:28 ` [Qemu-devel] [PATCH 01/12] piix4/ich9: do not raise SMI on ACPI enable/disable commands Paolo Bonzini
2015-06-18 16:28 ` Paolo Bonzini [this message]
2015-06-18 16:28 ` [Qemu-devel] [PATCH 03/12] kvm-all: put kvm_mem_flags to more work Paolo Bonzini
2015-06-18 16:28 ` [Qemu-devel] [PATCH 04/12] kvm-all: remove useless typedef Paolo Bonzini
2015-06-18 16:28 ` [Qemu-devel] [PATCH 05/12] kvm-all: move internal types to kvm_int.h Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 06/12] kvm-all: make KVM's memory listener more generic Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 07/12] kvm-all: add support for multiple address spaces Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 08/12] kvm-all: kvm_irqchip_create is not expected to fail Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 09/12] target-i386: register a separate KVM address space including SMRAM regions Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 10/12] pc_piix: rename kvm_enabled to smm_enabled Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 11/12] ich9: add smm_enabled field and arguments Paolo Bonzini
2015-06-18 16:30 ` [Qemu-devel] [PATCH 12/12] pc: add SMM property Paolo Bonzini
-- strict thread matches above, loose matches on Subject: below --
2015-06-05 14:31 [Qemu-devel] [PATCH 00/12] SMM part 2: KVM and -machine enablement Paolo Bonzini
2015-06-05 14:31 ` [Qemu-devel] [PATCH 02/12] target-i386: add support for SMBASE MSR and SMIs Paolo Bonzini
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