From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 08/12] arm: xlnx-zynqmp: Preface CPU variables with "apu"
Date: Fri, 19 Jun 2015 14:47:12 +0100 [thread overview]
Message-ID: <1434721636-25357-9-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1434721636-25357-1-git-send-email-peter.maydell@linaro.org>
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
The CPUs currently supported by zynqmp are the APU (application
processing unit) CPUs. There are other CPUs in Zynqmp so unqualified
"cpus" in ambiguous. Preface the variables with "APU" accordingly, to
prepare support adding the RPU (realtime processing unit) processors.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-ep108.c | 2 +-
hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++------------
include/hw/arm/xlnx-zynqmp.h | 4 ++--
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index b924f5e..7a98dd6 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -65,7 +65,7 @@ static void xlnx_ep108_init(MachineState *machine)
xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
xlnx_ep108_binfo.loader_start = 0;
- arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo);
+ arm_load_kernel(&s->soc.apu_cpu[0], &xlnx_ep108_binfo);
}
static QEMUMachine xlnx_ep108_machine = {
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 6b01965..353ecad 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -64,10 +64,10 @@ static void xlnx_zynqmp_init(Object *obj)
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
int i;
- for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
- object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
+ object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
"cortex-a53-" TYPE_ARM_CPU);
- object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
+ object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
&error_abort);
}
@@ -95,7 +95,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
- qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err) {
error_propagate((errp), (err));
@@ -121,38 +121,40 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
}
- for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
qemu_irq irq;
- object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
+ object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
if (i > 0) {
/* Secondary CPUs start in PSCI powered-down state */
- object_property_set_bool(OBJECT(&s->cpu[i]), true,
+ object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
"start-powered-off", &error_abort);
}
- object_property_set_int(OBJECT(&s->cpu[i]), GIC_BASE_ADDR,
+ object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
"reset-cbar", &err);
if (err) {
error_propagate((errp), (err));
return;
}
- object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+ object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
+ &err);
if (err) {
error_propagate((errp), (err));
return;
}
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
- qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
+ ARM_CPU_IRQ));
irq = qdev_get_gpio_in(DEVICE(&s->gic),
arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
- qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->gic),
arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
- qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
}
for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 79c2b0b..d042df1 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -27,7 +27,7 @@
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
TYPE_XLNX_ZYNQMP)
-#define XLNX_ZYNQMP_NUM_CPUS 4
+#define XLNX_ZYNQMP_NUM_APU_CPUS 4
#define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_NUM_UARTS 2
@@ -47,7 +47,7 @@ typedef struct XlnxZynqMPState {
DeviceState parent_obj;
/*< public >*/
- ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
+ ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
--
1.9.1
next prev parent reply other threads:[~2015-06-19 13:47 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-19 13:47 [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 01/12] target-arm: Add the Cortex-M4 CPU Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 02/12] hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 03/12] target-arm: Do not reset sysregs marked as ALIAS Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 04/12] target-arm/helper.c: define MPUIR register Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 05/12] target-arm: Add registers for PMSAv7 Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 06/12] target-arm: Implement PMSAv7 MPU Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 07/12] target-arm: Add support for Cortex-R5 Peter Maydell
2017-05-05 12:05 ` Philippe Mathieu-Daudé
2015-06-19 13:47 ` Peter Maydell [this message]
2015-06-19 13:47 ` [Qemu-devel] [PULL 09/12] arm: xlnx-zynqmp: Add boot-cpu property Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 10/12] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs Peter Maydell
2015-07-09 14:19 ` Paolo Bonzini
2015-06-19 13:47 ` [Qemu-devel] [PULL 11/12] semihosting: create SemihostingConfig structure and semihost.h Peter Maydell
2015-06-19 13:47 ` [Qemu-devel] [PULL 12/12] semihosting: add --semihosting-config arg sub-argument Peter Maydell
2015-06-19 17:32 ` [Qemu-devel] [PULL 00/12] target-arm queue Peter Maydell
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