From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40223) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6dzc-0008Nq-7T for qemu-devel@nongnu.org; Sun, 21 Jun 2015 08:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z6dza-0002cV-K8 for qemu-devel@nongnu.org; Sun, 21 Jun 2015 08:04:56 -0400 Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]:34326) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z6dza-0002cM-Cp for qemu-devel@nongnu.org; Sun, 21 Jun 2015 08:04:54 -0400 Received: by pdbki1 with SMTP id ki1so120437490pdb.1 for ; Sun, 21 Jun 2015 05:04:53 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id c16sm16627161pdl.61.2015.06.21.05.04.52 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 21 Jun 2015 05:04:53 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sun, 21 Jun 2015 21:56:16 +1000 Message-Id: <1434887787-4188-6-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1434887787-4188-1-git-send-email-edgar.iglesias@gmail.com> References: <1434887787-4188-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 05/16] target-microblaze: Tidy up the base-vectors property List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Alistair Francis Rename the "xlnx.base-vectors" string to "base-vectors" and move the base_vectors variable into the cfg struct. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- target-microblaze/cpu-qom.h | 3 ++- target-microblaze/cpu.c | 4 ++-- target-microblaze/helper.c | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index e08adb9..dd04199 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -56,12 +56,13 @@ typedef struct MicroBlazeCPUClass { typedef struct MicroBlazeCPU { /*< private >*/ CPUState parent_obj; - uint32_t base_vectors; + /*< public >*/ /* Microblaze Configuration Settings */ struct { bool stackprot; + uint32_t base_vectors; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index d3dad4a..0f805d3 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -120,7 +120,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); - env->sregs[SR_PC] = cpu->base_vectors; + env->sregs[SR_PC] = cpu->cfg.base_vectors; #if defined(CONFIG_USER_ONLY) env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ @@ -158,7 +158,7 @@ static const VMStateDescription vmstate_mb_cpu = { }; static Property mb_properties[] = { - DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), + DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 32896f4..69c3252 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -154,7 +154,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_ESR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->base_vectors + 0x20; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; break; case EXCP_MMU: @@ -194,7 +194,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); - env->sregs[SR_PC] = cpu->base_vectors + 0x20; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20; break; case EXCP_IRQ: @@ -235,7 +235,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] |= t; env->regs[14] = env->sregs[SR_PC]; - env->sregs[SR_PC] = cpu->base_vectors + 0x10; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10; //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -254,7 +254,7 @@ void mb_cpu_do_interrupt(CPUState *cs) if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; - env->sregs[SR_PC] = cpu->base_vectors + 0x18; + env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18; } else env->sregs[SR_PC] = env->btarget; break; -- 1.9.1