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From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Subject: [Qemu-devel] [PULL 02/20] hw/mips: Do not clear BEV for MIPS malta kernel load
Date: Fri, 26 Jun 2015 11:25:06 +0100	[thread overview]
Message-ID: <1435314324-8755-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1435314324-8755-1-git-send-email-leon.alrae@imgtec.com>

From: Matthew Fortune <matthew.fortune@imgtec.com>

The BEV flag controls whether the boot exception vector is still
in place when starting a kernel.  When cleared the exception vector
at EBASE (or hard coded address of 0x80000000) is used instead.

The early stages of the linux kernel would benefit from BEV still
being set to ensure any faults get handled by the boot rom exception
handlers.  This is a moot point for system qemu as there aren't really
any BEV handlers, but there are other good reasons to change this...

The UHI (semi-hosting interface) defines special behaviours depending
on whether an application starts in an environment with BEV set or
cleared. When BEV is set then UHI assumes that a bootloader is
relatively dumb and has no advanced exception handling logic.
However, when BEV is cleared then UHI assumes that the bootloader
has the ability to handle UHI exceptions with its exception handlers
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.

Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 786a8f0..a5d64d5 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -887,7 +887,7 @@ static void main_cpu_reset(void *opaque)
        read only location. The kernel location and the arguments table
        location does not change. */
     if (loaderparams.kernel_filename) {
-        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
+        env->CP0_Status &= ~(1 << CP0St_ERL);
     }
 
     malta_mips_config(cpu);
-- 
2.1.0

  parent reply	other threads:[~2015-06-26 10:25 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-26 10:25 [Qemu-devel] [PULL 00/20] target-mips queue Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 01/20] include/softmmu-semi.h: Make semihosting support 64-bit clean Leon Alrae
2015-06-26 10:25 ` Leon Alrae [this message]
2015-06-26 10:25 ` [Qemu-devel] [PULL 03/20] target-mips: remove identical code in different branch Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 04/20] target-mips: add Unified Hosting Interface (UHI) support Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 05/20] target-mips: convert host to MIPS errno values when required Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 06/20] target-mips: fix {RD, WR}PGPR in microMIPS Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 07/20] target-mips: add microMIPS TLBINV, TLBINVF Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 08/20] target-mips: remove an unused argument Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 09/20] target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 10/20] target-mips: rearrange gen_compute_compact_branch Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 11/20] target-mips: raise RI exceptions when FIR.PS = 0 Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 12/20] target-mips: signal RI for removed instructions in microMIPS R6 Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 13/20] target-mips: add microMIPS32 R6 opcode enum Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 14/20] target-mips: microMIPS32 R6 branches and jumps Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 15/20] target-mips: microMIPS32 R6 POOL32A{XF} instructions Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 16/20] target-mips: microMIPS32 R6 POOL32F instructions Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 17/20] target-mips: microMIPS32 R6 POOL32{I, C} instructions Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 18/20] target-mips: microMIPS32 R6 Major instructions Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 19/20] target-mips: microMIPS32 R6 POOL16{A, C} instructions Leon Alrae
2015-06-26 10:25 ` [Qemu-devel] [PULL 20/20] target-mips: add mips32r6-generic CPU definition Leon Alrae
2015-06-26 12:13 ` [Qemu-devel] [PULL 00/20] target-mips queue Peter Maydell

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