From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z9dkn-0004E5-4Z for qemu-devel@nongnu.org; Mon, 29 Jun 2015 14:26:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z9dkg-0005If-K5 for qemu-devel@nongnu.org; Mon, 29 Jun 2015 14:26:01 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34518) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z9dkg-0005B0-AM for qemu-devel@nongnu.org; Mon, 29 Jun 2015 14:25:54 -0400 From: Peter Maydell Date: Mon, 29 Jun 2015 19:25:45 +0100 Message-Id: <1435602345-32210-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH for-2.4] hw/intc/arm_gic_common.c: Reset all registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Peter Crosthwaite , patches@linaro.org The arm_gic_common reset function was missing reset code for several of the GIC's state fields: * bpr[] * abpr[] * priority1[] * priority2[] * sgi_pending[] * irq_target[] (SMP configurations only) These probably went unnoticed because most guests will either never touch them, or will write to them in the process of configuring the GIC before enabling interrupts. Signed-off-by: Peter Maydell --- The reason for using loops to set these array elements to 0 rather than using memset() is that to support "directly boot a kernel in NS on a TZ-aware GIC and CPU" we need to support resetting the priority registers (most notably the CPU priority mask) to 0x80 rather than 0. I found this via code review rather than because it triggered any kind of misbehaviour. last_active[] does not need any reset, I believe. hw/intc/arm_gic_common.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 044ad66..a64d071 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -123,7 +123,7 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp) static void arm_gic_common_reset(DeviceState *dev) { GICState *s = ARM_GIC_COMMON(dev); - int i; + int i, j; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { if (s->revision == REV_11MPCORE) { @@ -135,15 +135,30 @@ static void arm_gic_common_reset(DeviceState *dev) s->running_irq[i] = 1023; s->running_priority[i] = 0x100; s->cpu_ctlr[i] = 0; + s->bpr[i] = GIC_MIN_BPR; + s->abpr[i] = GIC_MIN_ABPR; + for (j = 0; j < GIC_INTERNAL; j++) { + s->priority1[j][i] = 0; + } + for (j = 0; j < GIC_NR_SGIS; j++) { + s->sgi_pending[j][i] = 0; + } } for (i = 0; i < GIC_NR_SGIS; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_EDGE_TRIGGER(i); } - if (s->num_cpu == 1) { + + for (i = 0; i < ARRAY_SIZE(s->priority2); i++) { + s->priority2[i] = 0; + } + + for (i = 0; i < GIC_MAXIRQ; i++) { /* For uniprocessor GICs all interrupts always target the sole CPU */ - for (i = 0; i < GIC_MAXIRQ; i++) { + if (s->num_cpu == 1) { s->irq_target[i] = 1; + } else { + s->irq_target[i] = 0; } } s->ctlr = 0; -- 1.9.1