From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>,
"Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
"Andreas Färber" <afaerber@suse.de>,
patches@linaro.org
Subject: [Qemu-devel] [PATCH 5/5] hw/arm/virt: Enable TZ extensions on the GIC if we are using them
Date: Tue, 30 Jun 2015 14:07:29 +0100 [thread overview]
Message-ID: <1435669649-3035-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1435669649-3035-1-git-send-email-peter.maydell@linaro.org>
If we're creating a board with support for TrustZone, then enable
it on the GIC model as well as on the CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4846892..084a551 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -360,7 +360,7 @@ static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
fdt_add_v2m_gic_node(vbi);
}
-static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
+static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, bool secure)
{
/* We create a standalone GIC v2 */
DeviceState *gicdev;
@@ -379,6 +379,9 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
* interrupts; there are always 32 of the former (mandated by GIC spec).
*/
qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
+ if (!kvm_irqchip_in_kernel()) {
+ qdev_prop_set_bit(gicdev, "has-security-extensions", secure);
+ }
qdev_init_nofail(gicdev);
gicbusdev = SYS_BUS_DEVICE(gicdev);
sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
@@ -875,7 +878,7 @@ static void machvirt_init(MachineState *machine)
create_flash(vbi);
- create_gic(vbi, pic);
+ create_gic(vbi, pic, vms->secure);
create_uart(vbi, pic);
--
1.9.1
next prev parent reply other threads:[~2015-06-30 13:21 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-30 13:07 [Qemu-devel] [PATCH 0/5] arm: enable TZ support for the GIC Peter Maydell
2015-06-30 13:07 ` [Qemu-devel] [PATCH 1/5] hw/intc/arm_gic_common.c: Reset all registers Peter Maydell
2015-06-30 13:07 ` [Qemu-devel] [PATCH 2/5] hw/intc/arm_gic_common: Provide property to make IRQs reset as NonSecure Peter Maydell
2015-06-30 13:07 ` [Qemu-devel] [PATCH 3/5] hw/arm/boot: Configure secure GIC to make IRQs NS if booting an NS kernel Peter Maydell
2015-06-30 19:01 ` Peter Crosthwaite
2015-06-30 19:42 ` Peter Maydell
2015-06-30 20:10 ` Peter Crosthwaite
2015-06-30 20:16 ` Peter Maydell
2015-06-30 20:24 ` Peter Crosthwaite
2015-07-02 12:41 ` Peter Maydell
2015-07-04 19:08 ` Peter Crosthwaite
2015-06-30 13:07 ` [Qemu-devel] [PATCH 4/5] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs Peter Maydell
2015-06-30 13:07 ` Peter Maydell [this message]
2015-07-07 13:27 ` [Qemu-devel] [PATCH 0/5] arm: enable TZ support for the GIC Peter Maydell
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