From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43414) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z9wQ7-0005TM-Ck for qemu-devel@nongnu.org; Tue, 30 Jun 2015 10:21:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z9wQ1-0006Kj-Ul for qemu-devel@nongnu.org; Tue, 30 Jun 2015 10:21:55 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34550) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z9wQ1-0006K4-Na for qemu-devel@nongnu.org; Tue, 30 Jun 2015 10:21:49 -0400 From: Peter Maydell Date: Tue, 30 Jun 2015 14:51:56 +0100 Message-Id: <1435672316-3311-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1435672316-3311-1-git-send-email-peter.maydell@linaro.org> References: <1435672316-3311-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 for-2.4 2/2] target-arm: Implement YIELD insn to yield in ARM and Thumb translators List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org Implement the YIELD instruction in the ARM and Thumb translators to actually yield control back to the top level loop rather than being a simple no-op. (We already do this for A64.) Signed-off-by: Peter Maydell --- target-arm/translate.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 971b6db..69ac18c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4080,6 +4080,10 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + case 1: /* yield */ + gen_set_pc_im(s, s->pc); + s->is_jmp = DISAS_YIELD; + break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_WFI; @@ -11459,6 +11463,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, case DISAS_WFE: gen_helper_wfe(cpu_env); break; + case DISAS_YIELD: + gen_helper_yield(cpu_env); + break; case DISAS_SWI: gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), default_exception_el(dc)); -- 1.9.1