From: Sergey Fedorov <serge.fdrv@gmail.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Sergey Fedorov <serge.fdrv@gmail.com>
Subject: [Qemu-devel] [PATCH] target-arm: fix write helper for TLBI ALLE1IS
Date: Tue, 30 Jun 2015 18:02:18 +0300 [thread overview]
Message-ID: <1435676538-31345-1-git-send-email-serge.fdrv@gmail.com> (raw)
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aa34159..b87afe7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
- .writefn = tlbiall_write },
+ .writefn = tlbiall_is_write },
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW,
--
1.9.1
next reply other threads:[~2015-06-30 15:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-30 15:02 Sergey Fedorov [this message]
2015-06-30 15:42 ` [Qemu-devel] [PATCH] target-arm: fix write helper for TLBI ALLE1IS Peter Maydell
2015-06-30 23:15 ` Edgar E. Iglesias
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