From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58692) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z9x3V-0007g0-3Q for qemu-devel@nongnu.org; Tue, 30 Jun 2015 11:02:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z9x3R-0002WL-Rr for qemu-devel@nongnu.org; Tue, 30 Jun 2015 11:02:37 -0400 Received: from mail-la0-x230.google.com ([2a00:1450:4010:c03::230]:33638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z9x3R-0002Vl-Kd for qemu-devel@nongnu.org; Tue, 30 Jun 2015 11:02:33 -0400 Received: by laar3 with SMTP id r3so17385068laa.0 for ; Tue, 30 Jun 2015 08:02:32 -0700 (PDT) From: Sergey Fedorov Date: Tue, 30 Jun 2015 18:02:18 +0300 Message-Id: <1435676538-31345-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH] target-arm: fix write helper for TLBI ALLE1IS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Sergey Fedorov TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Signed-off-by: Sergey Fedorov --- target-arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index aa34159..b87afe7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, .access = PL2_W, .type = ARM_CP_NO_RAW, - .writefn = tlbiall_write }, + .writefn = tlbiall_is_write }, { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW, -- 1.9.1