From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZBzht-0004ir-MT for qemu-devel@nongnu.org; Mon, 06 Jul 2015 02:16:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZBzhs-0004q6-RY for qemu-devel@nongnu.org; Mon, 06 Jul 2015 02:16:45 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:36001) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZBzhs-0004pt-LG for qemu-devel@nongnu.org; Mon, 06 Jul 2015 02:16:44 -0400 Received: by pacgz10 with SMTP id gz10so16199152pac.3 for ; Sun, 05 Jul 2015 23:16:44 -0700 (PDT) From: Serge Vakulenko Date: Sun, 5 Jul 2015 23:14:52 -0700 Message-Id: <1436163304-6167-5-git-send-email-serge.vakulenko@gmail.com> In-Reply-To: <1436163304-6167-1-git-send-email-serge.vakulenko@gmail.com> References: <1436163304-6167-1-git-send-email-serge.vakulenko@gmail.com> Subject: [Qemu-devel] [PATCH pic32 v3 04/16] pic32: add two MIPS processor variants: M4K and microAptivUP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Serge Vakulenko , Leon Alrae , Aurelien Jarno Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation. Signed-off-by: Serge Vakulenko --- target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index ddfaff8..8786321 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -190,6 +190,26 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_FMT, }, { + /* Configuration for Microchip PIC32MX microcontroller. */ + .name = "M4K", + .CP0_PRid = 0x00018700, + .CP0_Config0 = MIPS_CONFIG0 | (2 << CP0C0_K23) | (2 << CP0C0_KU) | + (1 << CP0C0_BM) | (1 << CP0C0_AR) | + (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = (1U << CP0C1_M) | (1 << CP0C1_CA) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = (1 << CP0C3_VEIC) | (1 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { .name = "4KEc", .CP0_PRid = 0x00019000, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | @@ -389,6 +409,32 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + /* Configuration for Microchip PIC32MZ microcontroller. */ + .name = "microAptivUP", + .CP0_PRid = 0x00019e00, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (1 << CP0C1_PC), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = (1 << CP0C3_M) | (1 << CP0C3_IPLW) | (1 << CP0C3_MCU) | + (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (1 << CP0C3_VEIC) | + (1 << CP0C3_VInt), + .CP0_Config4 = (1 << CP0C4_M), + .CP0_Config5 = (1 << CP0C5_NFExists), + .CP0_Config6 = 0, + .CP0_Config7 = 0, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, + { /* A generic CPU providing MIPS32 Release 5 features. FIXME: Eventually this should be replaced by a real CPU model. */ .name = "mips32r5-generic", -- 2.2.2