From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC5cM-0008QS-Pp for qemu-devel@nongnu.org; Mon, 06 Jul 2015 08:35:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZC5cK-0006Ae-Kr for qemu-devel@nongnu.org; Mon, 06 Jul 2015 08:35:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52518) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC5cK-0006AE-0m for qemu-devel@nongnu.org; Mon, 06 Jul 2015 08:35:24 -0400 From: Paolo Bonzini Date: Mon, 6 Jul 2015 14:34:56 +0200 Message-Id: <1436186108-29747-8-git-send-email-pbonzini@redhat.com> In-Reply-To: <1436186108-29747-1-git-send-email-pbonzini@redhat.com> References: <1436186108-29747-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 07/19] cpu-defs: Move out TB_JMP defines List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , Peter Crosthwaite From: Peter Crosthwaite These are not Architecture specific in any way so move them out of cpu-defs.h. tb-hash.h is an appropriate place as a leading user and their strong relationship to TB hashing and caching. Reviewed-by: Richard Henderson Signed-off-by: Peter Crosthwaite Message-Id: <43ceca65a3fa240efac49aa0bf604ad0442e1710.1433052532.git.crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini --- include/exec/cpu-defs.h | 8 -------- include/exec/tb-hash.h | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 247829c..98b9cff 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -56,14 +56,6 @@ typedef uint64_t target_ulong; #error TARGET_LONG_SIZE undefined #endif -/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for - addresses on the same page. The top bits are the same. This allows - TLB invalidation to quickly clear a subset of the hash table. */ -#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) -#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) -#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) -#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) - #if !defined(CONFIG_USER_ONLY) /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 diff --git a/include/exec/tb-hash.h b/include/exec/tb-hash.h index e0bd786..0f4e8a0 100644 --- a/include/exec/tb-hash.h +++ b/include/exec/tb-hash.h @@ -20,6 +20,14 @@ #ifndef EXEC_TB_HASH #define EXEC_TB_HASH +/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for + addresses on the same page. The top bits are the same. This allows + TLB invalidation to quickly clear a subset of the hash table. */ +#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) +#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) +#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) +#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) + static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) { target_ulong tmp; -- 2.4.3