From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53258) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZEdCV-0006RX-Ka for qemu-devel@nongnu.org; Mon, 13 Jul 2015 08:51:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZEdCS-00033z-8r for qemu-devel@nongnu.org; Mon, 13 Jul 2015 08:51:15 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:34489) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZEdCS-00033P-18 for qemu-devel@nongnu.org; Mon, 13 Jul 2015 08:51:12 -0400 Received: by pacan13 with SMTP id an13so15623456pac.1 for ; Mon, 13 Jul 2015 05:51:10 -0700 (PDT) From: "Edgar E. Iglesias" Date: Mon, 13 Jul 2015 22:50:57 +1000 Message-Id: <1436791864-4582-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v6 0/7] arm: Steps towards EL2 support round 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Hi, This is what is left of round 3 of our series towards support for EL2 for AArch64. Comments welcome! Best regards, Edgar v5 -> v6: * Fix spelling in comment, chose -> choose * Consistent layout of timer/counter trap checks * Rename and move gt_cnt_reset v4 -> v5: * Fix timer compare logic * Fix cval reads * Fix CNTHCTL exception priority * Comment on CNTHCTL reset value * Added AArch32 HYP timer regs * Reorder HYP timer regs * Use CP_CONST for RES0 HYP timer regs (EL3 but no EL2) v3 -> v4: * Add comment clarifing the unsigned/signed timer hit arithmetics * Replace GIC magic constants with macros * Slightly expanded commit messages v2 -> v3: * Use CP_ACCESS_TRAP_EL2 instead of setting target_el v1 -> v2: * Drop PAR_EL1 * Add AArch32 mappings of MAIR_EL2 * Add AArch32 mappings of TCR_EL2 * Add AArch32 mappings of SCTLR_EL2 * Add AArch32 mappings of TTBR0_EL2 * Add AArch32 mappings of TPIDR_EL2 * Add AArch32 mappings of CNTHCTL_EL2 * Add AArch32 mappings of CNTVOFF_EL2 * Tag CNTVOFF_EL2 and CNTVOFF as ARM_CP_IO * Rename TLIBALLE2 -> TLBI_ALLE2 * Break down TLB_LOCKDOWN to v7 level Edgar E. Iglesias (7): target-arm: Add CNTVOFF_EL2 target-arm: Add CNTHCTL_EL2 target-arm: Rename and move gt_cnt_reset target-arm: Pass timeridx as argument to various timer functions target-arm: Add the Hypervisor timer hw/arm/virt: Replace magic IRQ constants with macros hw/arm/virt: Connect the Hypervisor timer hw/arm/virt.c | 13 ++- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 + target-arm/cpu.h | 5 +- target-arm/helper.c | 251 ++++++++++++++++++++++++++++++++++++++++++++------- 5 files changed, 235 insertions(+), 37 deletions(-) -- 1.9.1